View STI5518_1253254.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

24 april 2001 c o n f i d e n t i a l ? 7170179 d STI5518 single-chip set-top box decoder with mp3 and hard disk drive support data sheet the information in this data sheet is subject to change without notice. n integrated 32-bit host cpu up to 81 mhz ? 2 kbytes of icache, 2 kbytes of dcache, and 4 kbytes of sram configurable as dcache. n audio decoder ? 5.1 channel dolby digital ? /mpeg-2 multi-channel decoding, 3 x 2-channel pcm outputs ? iec60958 -iec61937 digital output ? srs ? /trusurround ? ? dts ? digital out and mp3 decoding ? alignment beep for satellite dishes. n video decoder ? supports mpeg-2 mp@ml ? fully programmable zoom-in and zoom-out ? ntsc to pal conversion. n dvd and svcd subpicture decoder n high performance on-screen display ? 2 to 8 bits per pixel osd options ? anti-flicker, anti-flutter and anti-aliasing filters. n pal/ntsc/secam encoder ? rgb, cvbs, y/c and yuv outputs with 10-bit dacs ? macrovision ? 7.01/6.1 compatible (optional). n shared sdram memory interface ? 1 or 2x16-mbit, or 1x64-mbit 125 mh z sdram. n programmable cpu memory interface for sdram, rom, peripherals... n front-end interface ? dvd, vcd, svcd and cd-da compatible ? serial, parallel and atapi interfaces ? hardware sector filtering ? integrated css decryption and track buffer. n hardware transport-stream demultiplexor ? parallel/serial input ? des and dvb descramblers ? 32 pid support. n integrated peripherals ? 2 uarts, 2 smartcards, i 2 c controller, 3 pwm outputs, 3 capture timers ? modem support ? 44 bits of programmable i/o ? ir transmitter/receiver. n professional toolset support ? ansi c compiler and libraries. n 208 pin pqfp package. the STI5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes. it integrates a high-performance 32-bit cpu, a dedicated block for dvb/directv transport demultiplexing and descrambling, modules for mpeg-2 video and audio decoding with 3d-surround and mp3 support, advanced display and graphics features, a digital video encoder and all of the system peripherals required in a typical low-cost interactive receiver. to cover the needs of dvd-capable set-top boxes, STI5518 integration options include a css decryption block, a dolby digital audio decoder and macrovision copy protection. an atapi interface is built-in, supporting the glueless connection of standard hard disk drives. in this way, the STI5518 is ideal for set-top boxes featuring trick modes such as live tv recording, pausing and time-shifting. the STI5518 is backward compatible with the popular sti5500 set-top box decoder, allowing easy migration from the previous generation. the high level of integration in a single pqfp-208 package makes the STI5518 ideally suited for low-cost, high-volume set-top box applications. dma channels arbitrator front-end interface (sector processor & dvd decryption) 2k instruction cache 2k data cache and 4k sram st20 cpu 2 uart, 2 smartcard, pio, 3pwm, mafe interface ir blaster diagnostics controller and system services programmable cpu memory interface mpeg2 video sub-picture osd & background pal/ntsc & secam mpeg-2 multichannel dolby digital ? mp3, alignment beep
c o n f i d e n t i a l STI5518 2/294 7170179 d table of contents 1 architecture overview - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 1.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 1.2 central processor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10 1.3 mpeg video decoder - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10 1.4 audio decoder - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 1.5 ir transmitter/receiver - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 1.6 modem analog front-end interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 1.7 memory subsystem - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12 1.8 serial communication - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12 1.9 front-end interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 1.10 on-chip pll - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 1.11 diagnostic controller (dcu) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 1.12 interrupt subsystem - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 1.13 pal/ntsc/secam encoder - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 1.14 smartcard interfaces - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 1.15 pwm and counter module - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14 1.16 parallel i/o module - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14 2 pin data - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15 2.1 pin out - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15 2.2 pin list sorted by function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16 2.3 pins sorted by pin number - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 20 3 central processing unit - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27 3.1 registers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27 3.2 processes and concurrency - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 28 3.3 priority - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 29 3.4 process communications - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 30 3.5 timers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 30 3.6 traps and exceptions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 31 3.6.1 trap groups - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 32 3.6.2 events that can cause traps - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 33 3.6.3 trap handlers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 33 3.6.4 restrictions on trap handlers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 35 4 instruction set - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36 4.1 instruction cycles - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36 4.2 instruction characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 37 4.3 instruction-set tables - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 38 5 interrupt system - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45 5.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45 5.2 interrupt controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45 5.3 interrupt vector table - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 46 5.4 interrupt handlers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 47
c o n f i d e n t i a l STI5518 7170179 d 3/294 5.5 interrupt latency - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48 5.6 pre-emption and interrupt priority - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48 5.7 restrictions on interrupt handlers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48 5.8 interrupt level controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 49 5.9 interrupt assignments - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 50 6 memory map- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 51 6.1 overview - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 51 6.2 mapping - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 52 6.3 system memory use - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 55 7 memory - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 56 7.1 external memory - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 56 7.2 on-chip sram memory - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 56 7.3 caching - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 56 7.3.1 outline of operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 57 7.3.2 cache initialization - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 58 7.3.3 cache subsystem control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 58 7.3.4 data cache - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 58 7.3.5 instruction cache - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 59 7.3.6 cacheable and non-cacheable memory locations - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 60 8 programmable cpu memory interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 6 3 8.1 pin functions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 64 8.2 configuration list - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 68 8.3 external bus cycles - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 70 8.3.1 dram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 71 8.3.2 sdram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 75 8.3.3 sram or peripheral access cycles - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 78 8.3.4 wait - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 79 8.3.5 bank-width based address shifting - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 80 8.4 emi configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 80 8.5 default configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 80 9 system services - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 82 9.1 power-on hard reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 82 9.2 bootstrap - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 82 10 diagnostic controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 83 10.1 diagnostic hardware - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 83 10.2 access features - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 84 10.3 software debugging features - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 84 10.4 controlling the diagnostic controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 86 10.5 peeking and poking the host from the target - - - - - - - - - - - - - - - - - - - - - - - - - - - - 87 11 test access port - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 88 12 data flow- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 89 12.1 on-chip modules - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 89 12.2 video data flow - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 90
c o n f i d e n t i a l STI5518 4/294 7170179 d 12.3 audio data flow - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 91 13 front-end interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 92 13.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 92 13.2 serial interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 93 13.3 dvb-ci mode (optional) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 94 13.4 parallel interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 95 13.5 atapi interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 97 13.6 i2s interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 98 13.7 decryption cell - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 104 14 link - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 105 14.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 105 14.2 mpeg-2 & dss systems layers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 105 14.3 overview - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 107 14.4 detailed description - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 109 14.4.1 input interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 109 14.4.2 nrss interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 109 14.4.3 descrambler - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 111 14.4.4 sdav/p1394 interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 113 14.4.5 fram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 116 14.4.6 dma - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 120 14.4.7 clock recovery - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 123 14.4.8 interrupts - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 124 14.5 dvd/link data analyzer - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 128 14.6 hard disk drive buffer control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 132 15 mpeg video decoder - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 133 15.1 decoder operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 133 15.2 reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 133 15.3 bit buffer and start-code detection (video) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 134 15.3.1 bit buffer - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 134 15.3.2 start code detection - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 134 15.3.3 handling time-stamps - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 135 15.4 video decoding pipeline control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 136 15.5 quantization table loading - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 137 15.6 memory mapping of data - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 137 15.6.1 mapping 1 or 2 x 16-mbit sdram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 138 15.6.2 mapping 1 x 64-mbit sdram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 140 15.6.3 memory segments - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 142 15.6.4 arrangement of pixel-pairs inside a luma sdram row - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 142 15.6.5 arrangement of pixel-pairs inside a chroma sdram row - - - - - - - - - - - - - - - - - - - - - - - - - - - 143 15.7 using picture pointers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 143 15.8 video pipeline - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 144 15.8.1 decoding task - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 144 15.8.2 error recovery and missing macroblock concealment - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 145 15.9 pes parser - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 147 15.10 enhanced trick-modes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 148
c o n f i d e n t i a l STI5518 7170179 d 5/294 16 sub-picture decoder- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 16.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 16.2 buffer management and pointers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 151 16.3 operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 151 16.4 sub-picture display - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 153 16.4.1 look-up tables - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 153 16.4.2 sub-picture areas - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 153 17 overlay graphics and texts - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 154 17.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 154 17.2 buffer management - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 154 17.3 operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 155 17.4 display - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 155 18 display planes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 156 18.1 overview - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 156 18.2 background color plane - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 157 18.3 mpeg video plane - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 158 18.3.1 setting-up the display - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 158 18.3.2 sample rate converter - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 159 18.3.3 block-to-row converter - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 163 18.3.4 degradation mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 169 18.4 on-screen display (osd) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 169 18.4.1 using the osd - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 170 18.4.2 osd regions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 170 18.4.3 osd specification - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 171 18.4.4 osd region position - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 173 18.4.5 color palette - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 174 18.4.6 osd bit-map - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 177 18.4.7 osd block header format - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 177 18.4.8 osd specification block examples - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 178 18.4.9 mixing osd with video - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 181 18.4.10 anti-flicker and anti-flutter filters - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 181 18.4.11 osd active signal - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 182 18.5 sub-picture or cursor plane - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 183 18.6 mixing display planes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 183 18.6.1 4:2:2 output control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 185 19 sdram block move - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 186 20 digital encoder - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 187 20.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 187 20.2 video timing - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 187 20.3 reset procedure - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 192 20.4 master mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 192 20.5 slave modes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 193 20.5.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 193 20.5.2 line-based synchronization - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 193 20.5.3 frame-based synchronization - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 194 20.5.4 sync-in-data based synchronization - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 196 20.6 input demultiplexor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 198
c o n f i d e n t i a l STI5518 6/294 7170179 d 20.7 subcarrier generation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 199 20.8 burst insertion (pal and ntsc) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 200 20.9 subcarrier insertion (secam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 200 20.10 luminance encoding - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 201 20.11 chrominance encoding - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 203 20.12 composite video signal generation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 204 20.13 rgb and uv encoding - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 206 20.14 closed-captioning - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 207 20.15 cgms encoding - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 208 20.16 wss encoding - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 209 20.17 vps encoding - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 209 20.18 teletext encoding - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 209 20.19 line skip and line insert capability - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 212 20.20 cvbs, s-vhs, rgb and uv outputs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 212 21 teletext dma - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 214 21.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 214 21.2 teletext packet format - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 214 21.3 data transfer sequence - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 214 21.4 interrupt control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 215 21.5 teletext registers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 215 22 double triple video dac - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 216 22.1 description - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 216 22.2 input codes for video application - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 217 22.3 video output voltage level - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 217 22.4 video specifications and dac setup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 218 22.5 output-stage adaptation and amplification - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 218 23 audio decoder - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 219 23.1 features - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 219 23.2 architecture overview - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 220 23.3 decoding process - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 222 23.4 operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 222 23.5 decoding states - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 223 23.6 stream parsers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 224 23.7 decoding modes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 224 23.8 pcm output - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 229 23.9 spdif output - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 233 23.10 interrupts - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235 23.11 audio/video synchronization - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 236 23.12 pcm beep tone - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 237 23.13 audio trick modes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 238 23.13.1 description - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 238 23.13.2 slow forward - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 238 23.13.3 fast forward - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 239 23.13.4 spdif output for audio trick modes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 240
c o n f i d e n t i a l STI5518 7170179 d 7/294 24 external audio decoder interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 241 25 clock generator - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 242 25.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 242 25.2 system clocks - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 243 25.3 pcm clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 244 25.4 smartcard clocks - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 245 25.5 auxiliary clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 245 25.6 low-power, watchdog and power-down - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 246 26 mpegdma controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 247 27 block move dma - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 248 28 pwm and counter module - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 249 28.1 external interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 249 28.2 pwm outputs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 249 28.3 capture inputs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 249 28.4 compare (programmable timer) facilities - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 250 28.5 capture/compare counter, prescaling and clocking - - - - - - - - - - - - - - - - - - - - - - - - - 250 29 smartcard interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 251 29.1 external interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 251 29.2 smartcard clock generator - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 252 30 asynchronous serial controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 253 30.1 control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 253 30.1.1 resetting the fifos - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 253 30.1.2 transmission and reception - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 253 30.2 data frames - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 254 30.2.1 8-bit data frames - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 254 30.2.2 9-bit data frames - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 254 30.3 transmission - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255 30.3.1 transmission with fifos enabled - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255 30.3.2 double-buffered transmission - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 256 30.4 reception - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 256 30.4.1 hardware error detection - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 256 30.4.2 input buffering modes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 257 30.4.3 time-out mechanism - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 258 30.5 baud rate generation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 258 30.5.1 baud rates - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 258 30.6 interrupt control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 260 30.6.1 using the asc interrupts when fifos are disabled (double-buffered operation) - - - - - - - - - - - - - - - - 260 30.6.2 using the asc interrupts when fifos are enabled - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261 30.7 smartcard operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 262 30.7.1 control registers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 262 30.7.2 transmission - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 263 30.7.3 reception - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 264 30.7.4 divergence from iso smartcard specification - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 264
c o n f i d e n t i a l STI5518 8/294 7170179 d 31 synchronous serial controller- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 265 31.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 265 31.2 synchronous serial channel operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 266 31.3 ssc clocking - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 267 31.4 half-duplex operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 268 31.5 continuous transfers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 268 31.6 baud rates - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 269 31.7 hardware error detection capabilities - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 269 31.8 interrupt control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 270 31.9 i2c hardware configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 271 32 parallel input/output port - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 272 33 modem analog front-end interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 273 33.1 overview - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 273 33.2 using the mafeif to connect to a modem - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 273 33.3 software - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 274 33.3.1 data exchange - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 274 33.3.2 control/status exchange - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 274 34 infrared transmitter/receiver- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 275 34.1 introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 275 34.2 functional description - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 275 35 electrical specifications - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 278 35.1 absolute maximum ratings - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 278 35.2 dc electrical characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 278 35.2.1 static - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 278 35.2.2 st20 running at 60.75 mhz - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 279 35.2.3 st20 running at 81.0 mhz - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 279 35.3 ac test conditions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 280 35.4 operating conditions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 280 35.5 timing diagrams for io interfaces - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 281 35.5.1 input clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 281 35.5.2 smi interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 282 35.5.3 video interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 285 35.5.4 emi interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 286 35.5.5 tap interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 287 35.5.6 link interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 288 35.5.7 i2s interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 288 35.5.8 parallel interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 289 35.5.9 audio interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 289 35.5.10 atapi interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 290 36 package mechanical data - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 291 37 revision history - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 292 37.1 changes for rev d - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 292 37.2 changes for rev c - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 292 37.3 changes for rev b - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 292
c o n f i d e n t i a l STI5518 1 architecture overview 7170179 d 9/294 1 architecture overview 1.1 introduction the figure below shows the architecture of the STI5518. this chapter gives a brief overview of each of the functional blocks of the STI5518. figure 1 functional block diagram internal peripherals front-end & link interface dma central command port block move debug mpeg mpeg dmas communications arbiter cpu (c2+) clock generator refill control rid diagnostic controller dcache sram icache tap cpu arbiter cache subsystem st20 arbiter & memory controller i/f sdram block move cd fifos command i/f sdram arbiter (lmc) osd, sp decoder video filtering denc programmable cpu interface (emi) shared sdram interface (smi) video decoder and mixing jtag debugging interface analog/digital video output 16, 32 or 64 mbit sdram ext peripherals: flash, additional dram sdram qpsk, qam or cofdm receiver, atapi, dvd 2 uart & 2 smartcards i 2 c audio decoder audio out
c o n f i d e n t i a l 1 architecture overview STI5518 10/294 7170179 d 1.2 central processor the STI5518 central processing unit is a st20c2+ 32-bit processor core. it contains instruction processing logic, instruction and data pointers, and an operand register. it directly accesses the high-speed on-chip sram, which can store data or programs and uses the cache to reduce access time to off-chip program and data memory. the processor can access memory via the programmable cpu interface (often referred to as the emi) or the shared memory interface (smi), which is shared with the video, audio, sub-picture and osd decoders. 1.3 mpeg video decoder this is a real-time video compression processor supporting the mpeg-1 and mpeg-2 standards at video rates up to 720 x 480 x 60 hz and 720 x 576 x 50 hz. picture format conversion for display is performed by vertical and horizontal filters. user-defined bitmaps can be super-imposed on the display picture by using the on-screen display function. the display unit is part of the mpeg video decoder, it overlays the four display planes shown in the figure below. the display planes are normally overlaid in the order illustrated, with the background color at the back and the sub-picture at the front (used as a cursor plane). the sub-picture plane can alternatively be positioned between the osd and mpeg video planes where it can be used as a second on-screen display plane. figure 2 display planes on-screen display 08:23pm replay score stats replay score stats sub-picture plane 08:23pm replay score stats 08:23pm mpeg video overlaid planes background color
c o n f i d e n t i a l STI5518 1 architecture overview 7170179 d 11/294 1.4 audio decoder the audio decoder accepts: dolby digital, mpeg-1 layers i, ii and iii, mpeg-2 layer ii 6-channel, pcm, cdda data formats; mpeg2 pes streams for mpeg-2, mpeg-1, dolby digital, mp3, and linear pcm (lpcm). the audio decoder supports dts ? digital out (dvd dts and cdda dts). spdif input data (iec-60958 or iec-61937 standards) is accepted if an external circuitry extracts the pcm clock from the stream. skip frame, repeat blocks and soft mute frame features can be used to synchronize audio and video data. pts audio extraction is also supported. the device outputs up to 6 channels of pcm data and appropriate clocks for external digital-to-analog converters. programmable downmix enables 1,2,3 or 4 channel outputs. data can be output in either i 2 s format or sony format. the decoder can format output data according to iec-60958 standard (for non compressed data: l/r channels, 16, 18, 20 and 24-bits) or iec-61937 standard (for compressed data), for f s = 96 khz, 48 khz, 44.1 khz or 32 khz. sampling frequencies of 96 khz, 48 khz, 44.1 khz, 32 khz and half sampling frequencies are supported. a downsampling filter (96 khz/48 khz) is available. the decoder supports dual mode for mpeg and dolby digital. it includes a dolby surround compatible downmix and a prologic decoder. a pink noise generator enables the accurate positioning of speakers for optimal surround sound setup. pcm beep tone is a special mode used for set top box. it generates a triangular signal of variable frequency and amplitude on the left and right channels. in global mute mode, the decoder decodes the incoming bitstream normally but the pcm and spdif outputs are softmuted. this mode is used to prepare a period of decoding mode, to synchronize audio and video data without hearing the audio. slow-forward and fast-forward trick modes are available for compressed and non-compressed data. the control interface of the decoder is activated via memory mapped registers in the st20 address space. 1.5 ir transmitter/receiver the STI5518 provides a pulse-position modulated signal for automatic vcr programming by the set-top box. the signal is output to the ir blast pin and an accessory jack pin, simultaneously. the pulse frequency, number of pulses (envelope length) and the total cycle time is controlled by registers. 1.6 modem analog front-end interface the modem analog front-end interface is used to transfer transmit and receive dac and adc samples between the memory and an external modem analog front-end (mafe), using a synchronous serial protocol. dma is used to transfer the sample data between memory buffers and the mafe interface module, with separate transmit and receive buffers and double buffering of the buffer pointers. fifos are used to take into account the access latency to memory, in a worst case system and to allow the use of bursts for memory bandwidth efficiency improvement. the v22 bis standard is supported.
c o n f i d e n t i a l 1 architecture overview STI5518 12/294 7170179 d 1.7 memory subsystem on-chip the on-chip memory includes 2kbytes of instruction cache, 2kbytes of data cache and 4kbytes of sram that can be optionally configured as data cache. the subsystem provides 240m/bytes of internal bandwidth, supporting pipelined 2- cycle internal memory access. the instruction and data caches are direct-mapped, with a write-back system for the data-cache. the caches support burst accesses to the external memories for refill and write-back. burst access increases the performance of page- mode dram memories. off-chip there are two off-chip memory interfaces: the external memory interface (emi) accessed by the st20 is used for the transfer of data and programs between the STI5518 and external peripherals, flash and additional sdram and dram. shared memory interface (smi) controls the movement of data between the STI5518 and 16, 32 or 64 mbits of sdram. this external sdram stores the display data generated by the mpeg decoder and cpu and the c2+ code data. the emi uses minimal external support logic to support memory subsystems, and accesses a 32 mbytes of physical address space (greater if sdram or dram is used) in four general purpose memory banks of 8 or 16 bits wide, 21 or 22 address lines, and byte select. for applications requiring extra memory, the emi supports this extra memory with zero external support logic, even for 16-bit sdram devices. the emi can be configured for a wide variety of timing and decode functions by the configuration registers. the timing of each of the four memory banks can be set separately, with different device types being placed in each bank with no need for external hardware. 1.8 serial communication asynchronous serial controllers the asynchronous serial controller (asc), also referred to as the uart interface, provides serial communication between the STI5518 and other microcontrollers, microprocessors or external peripherals. the STI5518 has four ascs, two of which are generally used by the smartcard controllers. eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. parity, framing, and overrun error detection increase data transfer reliability. transmission and reception of data can be double-buffered, or 16-deep fifos can be used. a mechanism to distinguish the address from the data bytes is included for multiprocessor communication. testing is supported by a loop-back option. a 16-bit baud-rate generator provides the asc with a separate serial clock signal. two ascs support full-duplex and 2 half-duplex asynchronous communication, where both the transmitter and the receiver use the same data frame format and the same baud rate. each asc can be set to operate in smartcard mode for use when interfacing to a smartcard. synchronous serial controller two synchronous serial controllers (ssc) provide high-speed interfaces to a wide variety of serial memories, remote control receivers and other microcontrollers. the sscs support all of the features of the serial peripheral interface bus (spi) and the i 2 c bus. the sscs can be programmed to interface to other serial bus standards. the sscs share pins with the parallel input/output (pio) ports, and support half-duplex synchronous communication.
c o n f i d e n t i a l STI5518 1 architecture overview 7170179 d 13/294 1.9 front-end interface the STI5518 can be connected to a front-end through the following interfaces: i 2 s interface; multi-format serial interface; multi-format parallel interface; atapi interface (for hard disk drives and dvd-roms) 1.10 on-chip pll the on-chip pll accepts 27 mhz input and generates all the internal high-frequency clocks needed for the cpu, mpeg and audio subsystems. 1.11 diagnostic controller (dcu) the st20 diagnostic controller unit (dcu) is used to boot the cpu and to control and monitor the chip systems via the standard ieee 1194.1 test access port. the dcu includes on-chip hardware with ice (in circuit emulation) and lsa (logic state analyzer) features to facilitate verification and debugging of software running on the on-chip cpu in real time. it is an independent hardware module with a private link from the host to support real-time diagnostics. 1.12 interrupt subsystem the interrupt system allows an on-chip module or external interrupt pin to interrupt an active process so that an interrupt handling process can be run. an interrupt can be signalled by one of the following: a signal on an external interrupt pin, a signal from an internal peripheral or subsystem, software asserting an interrupt in the pending register. interrupts are implemented by an on-chip interrupt controller and an on-chip interrupt-level controller. the interrupt controller supports eight prioritized interrupts as inputs and manages the pending interrupts. this allows the nesting of pre-emptive interrupts for real-time system design. each interrupt can be programmed to be at a lower or higher priority than the high priority process queue. 1.13 pal/ntsc/secam encoder the integrated digital encoder converts a multiplexed 4:2:2 or 4:4:4 ycbcr stream into a standard analog baseband pal/ntsc or secam signal and into rgb, yuv, yc and cvbs components. the encoder can perform closed-caption, cgms encoding, and allows macrovision tm 7.01/6.1 copy protection. the denc is able to encode teletext according to the ? ccir/itu-r broadcast teletext system b ? specification, also known as ? world system teletext ? . in dvb applications, teletext data is embedded within dvb streams as mpeg data packets. it is the responsibility of the software to handle incoming data packets and in particular to store teletext packets in a buffer, which then passes them to the denc on request. 1.14 smartcard interfaces two smartcard interfaces support smartcards compliant with iso7816-3. each interface is has a uart (asc), a dedicated programmable clock generator, and eight bits of parallel io port.
c o n f i d e n t i a l 1 architecture overview STI5518 14/294 7170179 d 1.15 pwm and counter module the pwm and counter module provides three pwm encoder outputs, three pwm decoder (capture) inputs and four programmable timers. each capture input can be programmed to detect rising edge, falling edge, both edges or neither edge (disabled). these facilities are clocked by two independent clo cks, one for pwm outputs and one for capture inputs/timers. the pwm counter is 8-bit, with 8-bit registers to set the output-high time. the capture/compare counter and the compare and capture registers are 32-bit. the module generates a single interrupt signal. 1.16 parallel i/o module 44 bits of parallel i/o are configured in 6 ports, and each bit is programmable as output or input. the output can be configured as a totem-pole or open-drain driver. the input compare logic can generate an interrupt on any change of any input bit. many parallel io have alternate functions and can be connected to an internal peripheral signal such as a uart or ssc.
c o n f i d e n t i a l STI5518 2 pin data 7170179 d 15/294 2 pin data 2.1 pin out 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 pio2[4] pio2[3] pio2[2] pio2[1] pio2[0] trigger_out trigger_in pio1[5] pio1[4] vss vdd2_5 pio1[3] pio1[2] pio1[1] pio1[0] pio0[7] pio0[6] pio0[5] pio0[4] pio0[3] pio0[2] pio0[1] pio0[0] vss vdd3_3 cpu_adr[21] cpu_adr[20] cpu_adr[19] cpu_adr[18] cpu_adr[17] cpu_adr[16] cpu_adr[15] cpu_adr[14] cpu_adr[13] cpu_adr[12] cpu_adr[11] vss vdd2_5 cpu_adr[10] cpu_adr[9] cpu_adr[8] cpu_adr[7] cpu_adr[6] cpu_adr[5] cpu_adr[4] cpu_adr[3] cpu_adr[2] cpu_adr[1] vss vdd3_3 cpu_data[15] cpu_data[14] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 pio2[5] pio2[6] pio2[7] vdd3_3 vss pio3[0] pio3[1] pio3[2] pio3[3] pio3[4] pio3[5] pio3[6] pio3[7] vdd2_5 vss b_data b_bclk b_flag b_sync pio5[0] pio5[1] pio5[2] vdd_rgb vss_rgb b_out g_out r_out v_ref_rg i_ref_rg vdd_ycc vss_ycc y_out c_out cv_out v_ref_yc i_ref_yc vdd2_5 vss pio4[0] pio4[1] pio4[2] pio4[3] pio4[4] pio4[5] pio4[6] pio4[7] vdd3_3 vdd_pcm vss_pcm vss dac_sclk dac_pcmout0 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 cpu_data[13] cpu_data[12] cpu_data[11] cpu_data[10] cpu_data[9] cpu_data[8] vss vdd2_5 cpu_data[7] cpu_data[6] cpu_data[5] cpu_data[4] cpu_data[3] cpu_data[2] cpu_data[1] cpu_data[0] cpu_cas1 cpu_cas0 cpu_ras1 vss vdd3_3 cpu_ce[0] cpu_ce[1] cpu_ce[2] cpu_ce[3] cpu_wait cpu_rw cpu_be[1] cpu_be[0] i rq[0] irq[1] irq[2] reset vss_pll vdd_pll vss pix_clk vdd2_5 cpu_proclk cpu_oe pwm0 pwm1 pwm2 tck tdi tdo tms trst vss vdd3_3 auxclk pio5[5] dac_pcmout1 dac_pcmout2 dac_pcmclk dac_lrclk spdif_out smi_adr[4] smi_adr[5] smi_adr[6] smi_adr[7] smi_adr[8] smi_adr[9] vdd2_5 vss smi_adr[3] smi_adr[2] smi_adr[1] smi_adr[0] smi_adr[10] smi_adr[11] smi_adr[12] smi_adr[13] smi_cs[0] smi_cs[1] smi_ras smi_cas smi_we smi_dqml smi_dqmu vdd3_3 smi_clkin vss smi_data[0] smi_data[1] smi_data[2] smi_data[3] smi_data[4] smi_data[5] smi_data[6] smi_data[7] smi_data[8] smi_data[9] vdd2_5 smi_clkout vss smi_data[10] smi_data[11] smi_data[12] smi_data[13] smi_data[14] smi_data[15] pio5[3] pio5[4] 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 pqfp 208 (rev f) STI5518
c o n f i d e n t i a l 2 pin data STI5518 16/294 7170179 d 2.2 pin list sorted by function alternate functions printed in italic show a suggested use of the pio; alternate functions not printed in italic are multiplexed with a specific hardware. pin number pin name main function alternate function type input output audio dac 51 dac_sclk over sampling clock ext_aud_clk o 52 dac_pcmout0 pcm output 0 ext_aud_data o 53 dac_pcmout1 pcm output 1 ext_aud_req i/o 54 dac_pcmout2 pcm output 2 o 55 dac_pcmclk pcm clock i/o 56 dac_lrclk left/right clock ext_aud_wclk o 57 spdif_out spdif output o 48 vdd_pcm vdd freq synthesizer=2.5v pwr 2.5v 49 vss_pcm vss freq synthesizer=gnd pwr clock & reset 124 reset chip reset i 122 vdd_pll vdd pll=2.5v pwr 2.5v 123 vss_pll gnd pll=gnd pwr 120 pix _clk 27 mhz main clock i pios and communication 186 pio0[0] pio0[0] uart0_data (sc0_data) i/o 187 pio0[1] pio0[1] ttx_in_clock atapi_rd i/o 188 pio0[2] pio0[2] atapi_wr i/o 189 pio0[3] pio0[3] sc0_clock i/o 190 pio0[4] pio0[4] sc0_rst i/o 191 pio0[5] pio0[5] sc0_cmd_vcc i/o 192 pio0[6] pio0[6] sc0_data_dir i/o 193 pio0[7] pio0[7] sc0_detect i/o 194 pio1[0] pio1[0] ssc0_data (mtsrout/mrstin) i/o 195 pio1[1] pio1[1] ssc0_clock i/o 196 pio1[2] pio1[2] sc external clock para_dvalid i/o 197 pio1[3] pio1[3] uart2_txd i/o 200 pio1[4] pio1[4] uart2_rxd i/o 201 pio1[5] pio1[5] para_sync uart1_txd i/o 202 trigger_in trigger input for dcu i/o 203 trigger_out trigger output for dcu i/o 204 pio2[0] pio2[0] uart3_data (sc1_data) i/o 205 pio2[1] pio2[1] uart1_rxd mafeif_dout para_req i/o table 1 pins sorted by function
c o n f i d e n t i a l STI5518 2 pin data 7170179 d 17/294 206 pio2[2] pio2[2] para_str mafeif_hc1 i/o 207 pio2[3] pio2[3] sc1_clock i/o 208 pio2[4] pio2[4] sc1_rst i/o 1 pio2[5] pio2[5] sc1_cmd_vcc i/o 2 pio2[6] pio2[6] sc1_data_dir i/o 3 pio2[7] pio2[7] sc1_detect i/o 6 pio3[0] pio3[0] mafeif_sclk para_data{0] i/o 7 pio3[1] pio3[1] mafeif_din para_data[1] i/o 8 pio3[2] pio3[2] mafeif_fsi para_data[2] i/o 9 pio3[3] pio3[3] capture_in0 para_data[3] i/o 10 pio3[4] pio3[4] capture_in1 para_data[4] uart1 rts (rts1) i/o 11 pio3[5] pio3[5] capture_in2 para_data[5] uart2 rts (rts2) i/o 12 pio3[6] pio3[6] para_data[6] uart1 cts (cts1) comp_out1 i/o 13 pio3[7] pio3[7] para_data[7] uart2 cts (cts2) comp_out0 i/o 39-46 pio4[0:7] pio4[0:7] yc[0:7] i/o 20 pio5[0] pio5[0] b_wclk i/o ssc1_data/ nrss_clock 1 21 pio5[1] pio5[1] b_v4 nrss_out 2 and 1 i/o ssc1_clock 22 pio5[2] pio5[2] irb_irinput/nrss_in 2 i/o sdav_clk/ p1394_clk 3 103 pio5[3] 4 pio5[3] irb_uhfinput 4 i/o sdav_data 3 104 pio5[4] pio5[4] irb_driveppmsignal i/o sdav_dir / p1394_p_clk 3 105 pio5[5] pio5[5] irb_drive0orz 5 (jack) i/o osc_in_clk 3 auxiliary clock 106 auxiliary clock o emi interface 161-170 cpu_adr[1:10] address[1:10] o 173-183 cpu_adr[11:21] address[11:21] o 141-148 cpu_data[0:7] data[0:7] i/o pin number pin name main function alternate function type input output table 1 pins sorted by function
c o n f i d e n t i a l 2 pin data STI5518 18/294 7170179 d 151-158 cpu_data[8:15] data[8:15] i/o 138 cpu_ras1 dram ras not_sdram_cs1 chipsel. bank3 i/o 131 cpu_wait wait state i 130 cpu_rw read-not-write not_sdram_we o 128 cpu_be[0] byte 0 enable dqm[0] o 129 cpu_be[1] byte 1 enable dqm[1] o 139 cpu_cas0 dram cas 0 sdram_cas/ cpu_adr[22] o 140 cpu_cas1 dram not_sdram_cs0 o 135 cpu_ce[0] dram ras 0 sdram_ras notchipselbank0 o 134 cpu_ce[1] chip sel. bank 1 o 133 cpu_ce[2] chip sel. bank 2 o 132 cpu_ce[3] chip sel. bank 3 cs_sub_bank3 o 118 cpu_proclk emi clock o 117 cpu_oe output enable i/o interrupt 127 irq[0] irq[0] (servo_irq) i 126 irq[1] irq[1] (atapi irq) i 125 irq[2] irq[2] (md_irq) i timers 116 pwm0 pulse width modulator 0 hsync i/o 115 pwm1 pulse width modulator 1 boot_from_rom 6 i/o 114 pwm2 pulse width modulator 2 vsync i/o jtag 113 tck test clock i 112 tdi test data in i 111 tdo test data out o 110 tms test mode select i 109 trst 7 te s t r e se t i front-end 16 b_data i 2 s data fec_data i 17 b_bclk i 2 s bit clock fec_b_clk i 18 b_flag i 2 s error flag dvd fec_d_valid (dvd) fec_p_clk (dvb/dss) i 19 b_sync i 2 s sector/abs time fec_p_start (dvd) fec_error (dvb/ dss) i video dac 27, 26, 25 r_out, g_out, b_out r_out, g_out, b_out o pin number pin name main function alternate function type input output table 1 pins sorted by function
c o n f i d e n t i a l STI5518 2 pin data 7170179 d 19/294 32, 33, 34 y_out, c_out, cv_out y_out, c_out, cv_out o 29 i_ref_rgb rgb dac reference current i 28 v_ref_rgb rgb dac reference voltage i 36 i_ref_ycc ycc dac reference current i 35 v_ref_ycc ycc dac reference voltage i 23 vdd_rgb vdda_rgb=2.5v pwr 2.5v 24 vss_rgb vssa_rgb=gnd pwr 30 vdd_ycc vdda_ycc=2.5v pwr 2.5v 31 vss_ycc vssa_ycc=gnd pwr shared memory interface 69-66 smi_adr[0:3] address bus sdram o 58-63 smi_adr[4:9] address bus sdram o 70-73 smi_adr [10:13] address bus sdram o 84-93, 97-102 smi_data[0:15] data bus sdram i/o 74, 75 smi_cs[0,1] chip select bank 0,1 o 76 smi_ras ras sdram o 77 smi_cas cas sdram o 78 smi_we sdram write enable o 79, 80 smi_dqml, u dq mask en low, up o 82 smi_clkin sdram clock in i 95 smi_clkout sdram clock out o power supply 4, 47, 81, 107, 136, 159, 184 vdd3_3 3.3 v power supply pwr 14, 37, 64, 94, 119, 149, 171, 198 vdd2_5 2.5v power supply pwr 5, 15, 38, 50, 65, 83, 96, 108, 121, 137, 150, 160, 172, 185, 199 vss ground pwr 1. fei_cfg bits 8 and 9 must be programmed according to the required nrss configuration. 2. the nrss_in and nrss_out pins are swapped around on the STI5518 compared to the sti5508. 3. register lnk_sdav_conf bit 22 (sde) must be set to 1 to validate the output path. 4. inverted. attention! the pio input is also inverted. 5. the pio must be configured in open drain. 6. boot_from_rom is active during reset. 7. tie low whenever jtag is not used. pin number pin name main function alternate function type input output table 1 pins sorted by function
c o n f i d e n t i a l 2 pin data STI5518 20/294 7170179 d 2.3 pins sorted by pin number pin n pin name main function alternate function dir func. input output left side 1 pio2[5] pio2[5] sc1_cmd_vcc i/o 2 pio2[6] pio2[6] sc1_data_dir i/o 3 pio2[7] pio2[7] sc1_detect i/o 4 vdd3_3 3.3 v power supply power 5 vss ground power 6 pio3[0] pio3[0] mafeif_sclk para_data{0] i/o 7 pio3[1] pio3[1] mafeif_din para_data[1] i/o 8 pio3[2] pio3[2] mafeif_fsi para_data[2] i/o 9 pio3[3] pio3[3] capture_in0 para_data[3] i/o 10 pio3[4] pio3[4] capture_in1 para_data[4] uart1 rts (rts1) i/o 11 pio3[5] pio3[5] capture_in2 para_data[5] uart2 rts (rts2) i/o 12 pio3[6] pio3[6] para_data[6] uart1 cts (cts1) comp_out1 i/o 13 pio3[7] pio3[7] para_data[7] uart2 cts (cts2) comp_out0 i/o 14 vdd2_5 2.5v power supply power 15 vss ground power 16 b_data i 2 s data fec_data i 17 b_bclk i 2 s bit clock fec_b_clk i 18 b_flag i 2 s error flag dvd fec_d_valid (dvd) fec_p_clk (dvb/dss) i 19 b_sync i 2 s sector/abs time fec_p_start (dvd) fec_error (dvb/ dss) i 20 pio5[0] pio5[0] b_wclk i/o ssc1_data/ nrss_clock 1 21 pio5[1] pio5[1] b_v4 nrss_out 2 and 1 i/o ssc1_clock 22 pio5[2] pio5[2] irb_irinput/nrss_in 2 i/o sdav_clk/ p1394_clk 3 23 vdd_rgb vdda_rgb=2.5v power 24 vss_rgb vssa_rgb=gnd power 25 b_out b output o table 2 pins sorted by number
c o n f i d e n t i a l STI5518 2 pin data 7170179 d 21/294 26 g_out g output o 27 r_out r output o 28 v_ref_rgb rgb dac reference voltage i 29 i_ref_rgb rgb dac reference current i 30 vdd_ycc vdda_ycc=2.5v power 31 vss_ycc vssa_ycc=gnd power 32 y_out y output o 33 c_out c output o 34 cv_out cv output o 35 v_ref_ycc ycc dac reference voltage i 36 i_ref_ycc ycc dac reference current i 37 vdd2_5 2.5v power supply power 38 vss ground power 39 pio4[0] pio4[0] yc[0] i/o 40 pio4[1] pio4[1] yc[1] i/o 41 pio4[2] pio4[2] yc[2] i/o 42 pio4[3] pio4[3] yc[3] i/o 43 pio4[4] pio4[4] yc[4] i/o 44 pio4[5] pio4[5] yc[5] i/o 45 pio4[6] pio4[6] yc[6] i/o 46 pio4[7] pio4[7] yc[7] i/o 47 vdd3_3 3.3 v power supply power 48 vdd_pcm vdd freq synthesizer=2.5v power 49 vss_pcm vss freq synthesizer=gnd power 50 vss ground power 51 dac_sclk sampling clock ext_aud_clk o 52 dac_pcmout0 pcm output 0 ext_aud_data o bottom side 53 dac_pcmout1 pcm output 1 ext_aud_req i/o 54 dac_pcmout2 pcm output 2 o 55 dac_pcmclk pcm clock i/o 56 dac_lrclk left/right clock ext_aud_wclk o 57 spdif_out spdif output o 58 smi_adr[4] address bus sdram o 59 smi_adr[5] adress bus sdram o 60 smi_adr[6] adress bus sdram o 61 smi_adr[7] adress bus sdram o 62 smi_adr[8] adress bus sdram o 63 smi_adr[9] adress bus sdram o 64 vdd2_5 2.5v power supply power pin n pin name main function alternate function dir func. input output table 2 pins sorted by number
c o n f i d e n t i a l 2 pin data STI5518 22/294 7170179 d 65 vss ground power 66 smi_adr[3] adress bus sdram o 67 smi_adr[2] adress bus sdram o 68 smi_adr[1] adress bus sdram o 69 smi_adr[0] adress bus sdram o 70 smi_adr[10] adress bus sdram o 71 smi_adr[11] adress bus sdram o 72 smi_adr[12] adress bus sdram o 73 smi_adr[13] adress bus sdram o 74 smi_cs[0] chip select bank 0 o 75 smi_cs[1] chip select bank 1 o 76 smi_ras ras sdram o 77 smi_cas cas sdram o 78 smi_we sdram write enable o 79 smi_dqml dq mask en low o 80 smi_dqmu dq mask en up o 81 vdd3_3 3.3 v power supply power 82 smi_clkin sdram clock in i 83 vss ground power 84 smi_data[0] data bus sdram i/o 85 smi_data[1] data bus sdram i/o 86 smi_data[2] data bus sdram i/o 87 smi_data[3] data bus sdram i/o 88 smi_data[4] data bus sdram i/o 89 smi_data[5] data bus sdram i/o 90 smi_data[6] data bus sdram i/o 91 smi_data[7] data bus sdram i/o 92 smi_data[8] data bus sdram i/o 93 smi_data[9] data bus sdram i/o 94 vdd2_5 2.5v power supply power 95 smi_clkout sdram clock out o 96 vss ground power 97 smi_data[10] data bus sdram i/o 98 smi_data[11] data bus sdram i/o 99 smi_data[12] data bus sdram i/o 100 smi_data[13] data bus sdram i/o 101 smi_data[14] data bus sdram i/o 102 smi_data[15] data bus sdram i/o 103 pio5[3] pio5[3] irb_uhfinput 4 i/o sdav_data 3 pin n pin name main function alternate function dir func. input output table 2 pins sorted by number
c o n f i d e n t i a l STI5518 2 pin data 7170179 d 23/294 104 pio5[4] pio5[4] irb_driveppm signal i/o sdav_dir / p1394_p_clk 3 right side 105 pio5[5] pio5[5] irb_drive0orz 5 (jack) i/o osc_in_clk 3 106 auxiliary clock o 107 vdd3_3 3.3 v power supply power 108 vss ground power 109 trst 6 te s t r e se t i 110 tms test mode select i 111 tdo test data out o 112 tdi test data in i 113 tck test clock i 114 pwm2 pulse width modulator 2 vsync i/o 115 pwm1 pulse width modulator 1 boot_from_rom 7 i/o 116 pwm0 pulse width modulator 0 hsync i/o 117 cpu_oe output enable i/o 118 cpu_proclk emi clock o 119 vdd2_5 2.5v power supply power 120 pix _clk 27 mhz main clock i 121 vss ground power 122 vdd_pll vdd pll=2.5v power 123 vss_pll gnd pll=gnd power 124 reset chip reset i 125 irq[2] irq[2] (md_irq) i 126 irq[1] irq[1] (atapi irq) i 127 irq[0] irq[0] (servo_irq) i 128 cpu_be[0] byte 0 enable dqm[0] o 129 cpu_be[1] byte 1 enable dqm[1] o 130 cpu_rw read-not-write not_sdram_we o 131 cpu_wait wait state i 132 cpu_ce[3] chip select bank 3 cs_sub_bank3 o 133 cpu_ce[2] chip select bank 2 o 134 cpu_ce[1] chip select bank 1 o 135 cpu_ce[0] dram ras 0 sdram_ras o 136 vdd3_3 3.3 v power supply power 137 vss ground power 138 cpu_ras1 dram ras 1 not_sdram_cs1 chipsel. bank3 i/o pin n pin name main function alternate function dir func. input output table 2 pins sorted by number
c o n f i d e n t i a l 2 pin data STI5518 24/294 7170179 d 139 cpu_cas0 dram cas 0 sdram_cas cpu_adr[22] o 140 cpu_cas1 dram cas 1 not_sdram_cs0 o 141 cpu_data[0] data[0] i/o 142 cpu_data[1] data[1] i/o 143 cpu_data[2] data[2] i/o 144 cpu_data[3] data[3] i/o 145 cpu_data[4] data[4] i/o 146 cpu_data[5] data[5] i/o 147 cpu_data[6] data[6] i/o 148 cpu_data[7] data[7] i/o 149 vdd2_5 2.5v power supply power 150 vss ground power 151 cpu_data[8] data[8] i/o 152 cpu_data[9] data[9] i/o 153 cpu_data[10] data[10] i/o 154 cpu_data[11] data[11] i/o 155 cpu_data[12] data[12] i/o 156 cpu_data[13] data[13] i/o top side 157 cpu_data[14] data[14] i/o 158 cpu_data[15] data[15] i/o 159 vdd3_3 3.3 v power supply power 160 vss ground power 161 cpu_adr[1] address[1] o 162 cpu_adr[2] address[2] o 163 cpu_adr[3] address[3] o 164 cpu_adr[4] address[4] o 165 cpu_adr[5] address[5] o 166 cpu_adr[6] address[6] o 167 cpu_adr[7] address[7] o 168 cpu_adr[8] address[8] o 169 cpu_adr[9] address[9] o 170 cpu_adr[10] address[10] o 171 vdd2_5 2.5v power supply power 172 vss ground power 173 cpu_adr[11] address[11] o 174 cpu_adr[12] address[12] o 175 cpu_adr[13] address[13] o 176 cpu_adr[14] address[14] o pin n pin name main function alternate function dir func. input output table 2 pins sorted by number
c o n f i d e n t i a l STI5518 2 pin data 7170179 d 25/294 177 cpu_adr[15] address[15] o 178 cpu_adr[16] address[16] o 179 cpu_adr[17] address[17] o 180 cpu_adr[18] address[18] o 181 cpu_adr[19] address[19] o 182 cpu_adr[20] address[20] o 183 cpu_adr[21] address[21] o 184 vdd3_3 3.3 v power supply power 185 vss ground power 186 pio0[0] pio0[0] uart0_data (sc0_data) i/o 187 pio0[1] pio0[1] ttx_in_clock atapi_rd i/o 188 pio0[2] pio0[2] atapi_wr i/o 189 pio0[3] pio0[3] sc0_clock i/o 190 pio0[4] pio0[4] sc0_rst i/o 191 pio0[5] pio0[5] sc0_cmd_vcc i/o 192 pio0[6] pio0[6] sc0_data_dir i/o 193 pio0[7] pio0[7] sc0_detect i/o 194 pio1[0] pio1[0] ssc0_data (mtsrout/mrstin) i/o 195 pio1[1] pio1[1] ssc0_clock i/o 196 pio1[2] pio1[2] sc external clock para_dvalid i/o 197 pio1[3] pio1[3] uart2_txd i/o 198 vdd2_5 2.5v power supply power 199 vss ground power 200 pio1[4] pio1[4] uart2_rxd i/o 201 pio1[5] pio1[5] para_sync uart1_txd i/o 202 trigger_in trigger input for dcu i/o 203 trigger_out trigger output for dcu i/o 204 pio2[0] pio2[0] uart3_data (sc1_data) i/o 205 pio2[1] pio2[1] uart1_rxd mafeif_dout para_req i/o 206 pio2[2] pio2[2] para_str mafeif_hc1 i/o 207 pio2[3] pio2[3] sc1_clock i/o 208 pio2[4] pio2[4] sc1_rst i/o 1. fei_cfg bits 8 and 9 must be programmed according to the required nrss configuration. 2. the nrss_in and nrss_out pins are swapped around on the STI5518 compared to the sti5508. 3. register lnk_sdav_conf bit 22 (sde) must be set to 1 to validate the output path. 4. inverted. attention! the pio input is also inverted. 5. the pio must be configured in open drain. pin n pin name main function alternate function dir func. input output table 2 pins sorted by number
c o n f i d e n t i a l 2 pin data STI5518 26/294 7170179 d 6. tie low whenever jtag is not used 7. boot_from_rom is active during reset.
c o n f i d e n t i a l STI5518 3 central processing unit 7170179 d 27/294 3 central processing unit the STI5518 central processing unit is a st20c2+ 32-bit processor core. it contains instruction processing logic, instruction and data pointers, and an operand register. it directly accesses the high-speed on-chip sram, which can store data or programs, and uses the cache to reduce access time to off-chip program and data memory. the cpu can access memory via the general purpose external memory interface (emi) or the local memory interface (lmi), which is shared with the mpeg decoder. the processor performs the following manipultations: fast integer-multiply - 4 cycle multiply; fast bit-shift - single cycle barrel shifter; byte and part-word handling; scheduling and interrupt support; 64-bit integer arithmetic support. the scheduler provides a single level of pre-emption. in addition, multi-level pre-emption is provided by the interrupt subsystem. additionally, there is a per-priority trap handler to improve the support for arithmetic errors and illegal instructions. 3.1 registers the cpu contains six registers which are used in the execution of a sequential integer process. the six registers are: workspace pointer (wptr) which points to an area of store where local data is kept. instruction pointer (iptr) which points to the next instruction to be executed. status register (status). areg, breg and creg registers which form an evaluation stack. the areg, breg and creg registers are the sources and destinations for most arithmetic and logical operations. loading a value into the stack pushes breg into creg, and areg into breg, before loading areg. storing a value from areg, pops breg into areg and creg into breg. creg is left undefined. expressions are evaluated on the evaluation stack, and instructions refer to the stack implicitly. for example, the add instruction adds the top two values in the stack and places the result on the top of the stack. the use of a stack removes the need for instructions to explicitly specify the location of their operands. no hardware mechanism is figure 3 registers used in sequential integer processes areg breg creg wptr iptr local data program registers
c o n f i d e n t i a l 3 central processing unit STI5518 28/294 7170179 d provided to detect that more than three values have been loaded onto the stack; it is easy for the compiler to ensure that this never happens. note that a location in memory can be accessed relative to the workspace pointer, enabling the workspace to be of any size. the use of shadow registers provides fast, simple and clean context switching. 3.2 processes and concurrency this section describes the default behavior of the cpu and it should be noted that the user can alter this behavior, for example by disabling timeslicing or installing a user scheduler. a process starts, performs a number of actions, and then either stops without completing or terminates complete. typically, a process is a sequence of instructions. the cpu can run several processes in parallel (concurrently). processes may be assigned either high or low priority, and there may be any number of each. the processor has a microcoded scheduler which enables any number of concurrent processes to be executed together, sharing the processor time. this removes the need for a software kernel, although kernels can still be written if desired. at any time, a process may be the scheduler operates in such a way that inactive processes do not consume any processor time. each active high priority process executes until it becomes inactive. the scheduler allocates a portion of the processor ? s time to each active low priority process in turn (see section section 3.3). active processes waiting to be executed are held in two linked lists of process work spaces, one of high priority processes and one of low priority processes. each list is implemented using two registers, one of which points to the first process in the list, the other to the last. in the linked process list shown below, process s is executing and p , q and r are active, awaiting execution. only the low priority process queue registers are shown; the high priority process ones behave in a similar manner. active - - - being executed interrupted by a higher priority process on a list waiting to be executed inactive - - - waiting to input waiting to output waiting until a specified time figure 4 linked process list p q r s areg breg creg wptr iptr fptrreg1 bptrreg1 registers local data iptr.s link.s iptr.s link.s iptr.s program
c o n f i d e n t i a l STI5518 3 central processing unit 7170179 d 29/294 each process runs until it has completed its action or is descheduled. in order for several processes to operate in parallel, a low priority process is only permitted to execute for a maximum of two timeslice periods. after this, the machine deschedules the current process at the next timeslicing point, adds it to the end of the low priority scheduling list and instead executes the next active process. the timeslice period is 1ms. there are only certain instructions at which a process may be descheduled. these are known as descheduling points. a process may only be timesliced at certain descheduling points. these are known as timeslicing points and are defined in such a way that the operand stack is always empty. this removes the need for saving the operand stack when timeslicing. as a result, an expression evaluation can be guaranteed to execute without the process being timesliced part way through. whenever a process is unable to proceed, its instruction pointer is saved in the process workspace and the next process taken from the list. the processor core provides a number of special instructions to support the process model, including startp (start process) and endp (end process). when a main process executes a parallel construct, startp is used to create the necessary additional concurrent processes. a startp instruction creates a new process by adding a new workspace to the end of the scheduling list, enabling the new concurrent process to be executed together with the ones already being executed. when a process is made active it is always added to the end of the list, and thus cannot pre-empt processes already on the same list. the correct termination of a parallel construct is assured by use of the endp instruction. this uses a data structure that includes a counter of the parallel construct components which have still to terminate. the counter is initialized to the number of components before the processes are started. each component ends with an endp instruction which decrements and tests the counter. for all but the last component, the counter is non zero and the component is descheduled. for the last component, the counter is zero and the main process continues. 3.3 priority the following section describes ? default ? behavior of the cpu and it should be noted that the user can alter this behavior, for example, by disabling timeslicing and priority interrupts. the processor can execute processes at one of two priority levels, one level for urgent (high priority) processes, one for less urgent (low priority) processes. a high priority process will always execute in preference to a low priority process if both are able to do so. high priority processes are expected to execute for a short time. if one or more high priority processes are active, then the first on the queue is selected and executes until it has to wait for a communication, a timer input, or until it completes processing. if no process at high priority is active, but one or more processes at low priority are active, then one is selected. low priority processes are periodically timesliced to provide an even distribution of processor time between tasks which use a lot of computation. if there are n low priority processes, then the maximum latency from the time at which a low priority process becomes active to the time when it starts processing is the order of 2 n timeslice periods. it is then able to execute for between one and two timeslice periods, less any time taken by high priority processes. this assumes that no process monopolizes the time of the cpu; i.e. it has frequent timeslicing points. function high priority low priority pointer to front of active process list fptrreg0 fptrreg1 pointer to back of active process list bptrreg0 bptrreg1 table 3 priority queue control registers
c o n f i d e n t i a l 3 central processing unit STI5518 30/294 7170179 d the specific condition for a high priority process to start execution is that the cpu is idle or running at low priority and the high priority queue is non-empty. if a high priority process becomes able to run while a low priority process is executing, the low priority process is temporarily stopped and the high priority process is executed. the state of the low priority process is saved into ? shadow ? registers and the high priority process is executed. when no further high priority processes are able to run, the state of the interrupted low priority process is re-loaded from the shadow registers and the interrupted low priority process continues executing. instructions are provided on the processor core to allow a high priority process to store the shadow registers to memory and to load them from memory. instructions are also provided to allow a process to exchange an alternative process queue for either priority process queue. these instructions allow extensions to be made to the scheduler for custom run-time kernels. a low priority process may be interrupted after it has completed execution of any instruction. in addition, to minimize the time taken for an interrupting high priority process to start executing, the potentially time consuming instructions are interruptible. also some instructions may be aborted, and are restarted when the process next becomes active (refer to chapter 4: instruction set on page 36). 3.4 process communications communication between processes takes place over channels, and is implemented in hardware. communication is point-to-point, synchronized and unbuffered. as a result, a channel needs no process queue, no message queue and no message buffer. a channel between two processes executing on the same cpu is implemented by a single word in memory; a channel between processes executing on different processors is implemented by point-to-point links. the processor provides a number of operations to support message passing, the most important being in (input message) and out (output message). the in and out instructions use the address of the channel to determine whether the channel is internal or external. this means that the same instruction sequence can be used for both hard and soft channels, allowing a process to be written and compiled without knowledge of where its channels are implemented. communication takes place when both the inputting and outputting processes are ready. consequently, the process which first becomes ready must wait until the second one is also ready. the inputting and outputting processes only become active when the communication has completed. a process performs an input or output by loading the evaluation stack with, a pointer to a message, the address of a channel, and a count of the number of bytes to be transferred, and then executing an in or out instruction. 3.5 timers there are two 32-bit hardware timer clocks which ? tick ? periodically. these are independent of any on-chip peripheral real time clock. the timers provide accurate process timing, allowing processes to deschedule themselves until a specific time. one timer is accessible only to high priority processes and is incremented approximately every microsecond, cycling completely in approximately 4295 seconds. the other is accessible only to low priority processes and runs 64 times slower, giving 15625 ticks per second. it has a full period of approximately 76 hours. actual timer speeds are derived from the processor speed cpu_proclk and are given in the clocks chapter. the periods may be calculated as follows: high_priority_clock_period = 1 s nominal_speed / cpu_proclk _speed
c o n f i d e n t i a l STI5518 3 central processing unit 7170179 d 31/294 low_priority_clock_period = high_priority_clock_period x 64 the current value of the processor clock can be read by executing a ldtimer (load timer) instruction. a process can arrange to perform a tin (timer input), in which case it will become ready to execute after a specified time has been reached. the tin instruction requires a time to be specified. if this time is in the ? past ? then the instruction has no effect. if the time is in the ? future ? then the process is descheduled. when the specified time is reached the process becomes active. in addition, the ldclock (load clock), stclock (store clock) instructions allow total control over the clock value and the clockenb (clock enable), clockdis (clock disable) instructions allow each clock to be individually stopped and re- started. figure 5 shows two processes waiting on the timer queue, one waiting for time 21, the other for time 31. 3.6 traps and exceptions a software error, such as arithmetic overflow or array bounds violation, can cause an error flag to be set in the cpu. the flag is directly connected to the errorout pin. both the flag and the pin can be ignored, or the cpu stopped. stopping the cpu on an error means that the error cannot cause further corruption. as well as containing the error in this way it is possible to determine the state of the cpu and its memory at the time the error occurred. this is register function clockreg0 current value of high priority (level 0) process clock. clockreg1 current value of low priority (level 1) process clock. tnextreg0 indicates time of earliest event on high priority (level 0) timer queue. tnextreg1 indicates time of earliest event on low priority (level 1) timer queue. tptrreg0 high priority timer queue. tptrreg1 low priority timer queue. table 4 timer registers figure 5 timer registers clockreg0 tnextreg0 tptrreg0 work spaces program 5 21 31 empty comparator alarm 21
c o n f i d e n t i a l 3 central processing unit STI5518 32/294 7170179 d particularly useful for postmortem debugging where the debugger can be used to examine the state and history of the processor leading up to and causing the error condition. in addition, if a trap handler process is installed, a variety of traps/exceptions can be trapped and handled by software. a user supplied trap handler routine can be provided for each high/low process priority level. the handler is started when a trap occurs and is given the reason for the trap. the trap handler is not re-entrant and must not cause a trap itself within the same group. all traps can be individually masked. 3.6.1 trap groups the trap mechanism is arranged on a per priority basis. for each priority there is a handler for each group of traps, as shown in figure 6 . there are four groups of traps, as detailed below. breakpoint trap : the breakpoint instruction ( j0 ) calls the breakpoint routine via the trap mechanism. errors: the traps in this group are integererror and overflow . overflow represents arithmetic overflow, such as arithmetic results which do not fit in the result word. integererror represents errors caused when data is erroneous, for example when a range checking instruction finds that data is out of range. system operations : this group consists of the loadtrap , storetrap and illegalopcode traps. the illegalopcode trap is signalled when an attempt is made to execute an illegal instruction. the loadtrap and storetrap traps allow a kernel to intercept attempts by a monitored process to change or examine trap handlers or trapped process information. it enables a user program to signal to a kernel that it wishes to install a new trap handler. scheduler : the scheduler trap group consists of the externalchannel, internalchannel, timer, timeslice, run, signal, processinterrupt and queueempty traps. the processinterrupt trap signals that the machine has performed a priority interrupt from low to high. the queueempty trap indicates that there is no further executable work to perform. the other traps in this group indicate that the hardware scheduler wants to schedule a process on a process queue, with the different traps enabling the different sources of this to be monitored. the scheduler traps enable a software scheduler kernel to use the hardware scheduler to implement a multi-priority software scheduler. note that scheduler traps are different from other traps as they are caused by the micro-scheduler rather than by an executing process. figure 6 trap arrangement low priority traps high priority traps cpu error trap handler system operations trap handler scheduler trap handler breakpoint trap handler cpu error trap handler system operations trap handler scheduler trap handler breakpoint trap handler
c o n f i d e n t i a l STI5518 3 central processing unit 7170179 d 33/294 trap groups encoding is shown in below. these codes are used to identify trap groups to various instructions. in addition to the trap groups mentioned above, the causeerror flag in the status register is used to signal when a trap condition has been activated by the causeerror instruction. it can be used to indicate when trap conditions have occurred due to the user setting them, rather than by the system. 3.6.2 events that can cause traps ta b le 6 summarizes the events that can cause traps and gives the encoding of bits in the trap status and enable words. 3.6.3 trap handlers for each trap handler there is a trap handler structure and a trapped process structure. both the trap handler structure and the trapped process structure are in memory and can be accessed via instructions, see section section . the trap handler structure specifies what should happen when a trap condition is present, see . trap group code breakpoint 0 cpu errors 1 system operations 2 scheduler 3 table 5 trap group codes trap cause status/enable codes trap group comments breakpoint 0 0 when a process executes the breakpoint instruction ( j0 ) then it traps to its trap handler. integererror 1 1 integer error other than integer overflow - e.g. explicitly checked or explicitly set error. overflow 2 1 integer overflow or integer division by zero. illegalopcode 3 2 attempt to execute an illegal instruction. this is signalled when opr is executed with an invalid operand. loadtrap 4 2 when the trap descriptor is read with the ldtraph instruction or when the trapped process status is read with the ldtrapped instruction. storetrap 5 2 when the trap descriptor is written with the sttraph instruction or when the trapped process status is written with the sttrapped instruction. internalchannel 6 3 scheduler trap from internal channel. externalchannel 7 3 scheduler trap from external channel. timer 8 3 scheduler trap from timer alarm. timeslice 9 3 scheduler trap from timeslice. run 10 3 scheduler trap from runp (run process) or startp (start process). signal 11 3 scheduler trap from signal . processinterrupt 12 3 start executing a process at a new priority level. queueempty 13 3 caused by no process active at a priority level. causeerror 15 (status only) any, encoded 0-3 signals that the causeerror instruction set the trap flag. table 6 trap causes and status/enable codes
c o n f i d e n t i a l 3 central processing unit STI5518 34/294 7170179 d the trapped process structure saves some of the state of the process that was running when the trap was taken. in addition, for each priority, there is an enables register and a status register. the enables register contains flags to enable each cause of trap. the status register contains flags to indicate which trap conditions have been detected. the enables and status register bit encodings are given in table 6 . a trap will be taken at an interruptible point if a trap is set and the corresponding trap enable bit is set in the enables register. if the trap is not enabled then nothing is done with the trap condition. if the trap is enabled then the corresponding bit is set in the status register to indicate the trap condition has occurred. when a process takes a trap the processor saves the existing iptr , wptr , status and enables in the trapped process structure. it then loads iptr , wptr and status from the equivalent trap handler structure and ands the value in enables with the value in the structure. this allows the user to disable various events while in the handler, in particular a trap handler must disable all the traps of its trap group to avoid the possibility of a handler trapping to itself. the trap handler then executes. the values in the trapped process structure can be examined using the ldtrapped instruction (see section section ). when the trap handler has completed its operation it returns to the trapped process via the tret (trap return) instruction. this reloads the values saved in the trapped process structure and clears the trap flag in status . note that when a trap handler is started, areg , breg and creg are not saved. the trap handler must save the areg , breg , creg registers using stl (store local). comments location iptr iptr of trap handler process. base + 3 wptr wptr of trap handler process. a null wptr indicates that a trap handler has not been installed. base + 2 status contains the status register that the trap handler starts with. base + 1 enables a word which encodes the trap enable and global interrupt masks, which will be anded with the exist- ing masks to allow the trap handler to disable various events while it runs. base + 0 table 7 trap handler structure comments location iptr points to the instruction after the one that caused the trap condition. base + 3 wptr wptr of the process that was running when the trap was taken. base + 2 status the relevant trap bit is set, see for trap codes. base + 1 enables interrupt enables. base + 0 table 8 trapped process structure
c o n f i d e n t i a l STI5518 3 central processing unit 7170179 d 35/294 trap instructions trap handlers and trapped processes can be set up and examined via the ldtraph , sttraph , ldtrapped and sttrapped instructions. table 9 describes the instructions that may be used when dealing with traps. the first four instructions transfer data to/from the trap handler structures or trapped process structures from/to an area in memory. in these instructions areg contains the trap group code and breg points to the 4 word area of memory used as the source or destination of the transfer. in addition creg contains the priority of the handler to be installed/examined in the case of ldtraph or sttraph. ldtrapped and sttrapped apply only to the current priority. if the loadtrap trap is enabled then ldtraph and ldtrapped do not perform the transfer but set the loadtrap trap flag. if the storetrap trap is enabled then sttraph and sttrapped do not perform the transfer but set the storetrap trap flag. the trap enable masks are encoded by an array of bits (see ta b l e 6 ) which are set to indicate which traps are enabled. this array of bits is stored in the lower half-word of the enables register. there is an enables register for each priority. traps are enabled or disabled by loading a mask into areg with bits set to indicate which traps are to be affected and the priority to affect in breg . executing trapenb ors the mask supplied in areg with the trap enables mask in the enables register for the priority in breg . executing trapdis negates the mask supplied in areg and ands it with the trap enables mask in the enables register for the priority in breg . both instructions return the previous value of the trap enables mask in areg . 3.6.4 restrictions on trap handlers there are various restrictions that must be placed on trap handlers to ensure that they work correctly. trap handlers must not deschedule or timeslice. trap handlers alter the enables masks, therefore they must not allow other processes to execute until they have completed. trap handlers must have their enable masks set to mask all traps in their trap group to avoid the possibility of a trap handler trapping to itself. trap handlers must terminate via the tret (trap return) instruction . the only exception to this is that a scheduler kernel may use restart to return to a previously shadowed process. instruction meaning use ldtraph load trap handler load the trap handler from memory to the trap handler descriptor. sttraph store trap handler store an existing trap handler descriptor to memory. ldtrapped load trapped load replacement trapped process status from memory. sttrapped store trapped store trapped process status to memory. trapenb trap enable enable traps. trapdis trap disable disable traps. tret trap return used to return from a trap handler. causeerror cause error program can simulate the occurrence of an error. table 9 instructions which may be used when dealing with traps
c o n f i d e n t i a l 4 instruction set STI5518 36/294 7170179 d 4 instruction set this chapter provides information on the st20-c2+ instruction set. it contains tables listing all the instructions, and where applicable provides details of the number of processor cycles taken by an instruction. the instruction set has been designed for simple and efficient compilation of high-level languages. all instructions have the same format, designed to give a compact representation of the operations occurring most frequently in programs. each instruction consists of a single byte divided into two 4-bit parts. the four most significant bits (msb) of the byte are a function code and the four least significant bits (lsb) are a data value, as shown below. for further information on the instruction set refer to the st20c2/c4 instruction set manual (document number 72- trn-273). 4.1 instruction cycles timing information is available for some instructions. however, it should be noted that many instructions have ranges of timings which are data dependent. where included, timing information is based on the number of clock cycles assuming any memory accesses are to 2 cycle internal memory and no other subsystem is using memory. actual time will be dependent on the speed of external memory and memory bus availability. note that the actual time can be increased by: the instruction requiring a value on the register stack from the final memory read in the previous instruction ? the current instruction will stall until the value becomes available. the first memory operation in the current instruction can be delayed while a preceding memory operation completes - any two memory operations can be in progress at any time, any further operation will stall until the first completes. memory operations in current instructions can be delayed by access by instruction fetch or subsystems to the memory interface. there can be a delay between instructions while the instruction fetch unit fetches and partially decodes the next instruction ? this will be the case whenever an instruction causes the instruction flow to jump. note that the instruction timings given refer to ? standard ? behavior and may be different if, for example, traps are set by the instruction. figure 7 instruction format function data 7430
c o n f i d e n t i a l STI5518 4 instruction set 7170179 d 37/294 4.2 instruction characteristics table 12 on page 38 gives the basic function code of each of the primary instructions. where the operand is less than 16, a single byte encodes the complete instruction. if the operand is greater than 15, one prefix instruction ( pfix ) is required for each additional four bits of the operand. if the operand is negative the first prefix instruction will be nfix . examples of pfix and nfix coding are given in table 10 . any instruction which is not in the instruction set tables is an invalid instruction and is flagged illegal, returning an error code to the trap handler, if loaded and enabled. the notes column of the tables indicates the features of an instruction as described in table 11 . mnemonic function code memory code ldc #3 #4 #43 ldc #35 is coded as pfix #3 #2 #23 ldc #5 #4 #45 ldc #987 is coded as pfix #9 #2 #29 pfix #8 #2 #28 ldc #7 #4 #47 ldc -31 ( ldc #ffffffe1) is coded as nfix #1 #6 #61 ldc #1 #4 #41 table10prefix coding ident feature e instruction can set an integererror trap l instruction can cause a loadtrap trap s instruction can cause a storetrap trap o instruction can cause an overflow trap i interruptible instruction a instruction can be aborted and later restarted. d instruction can deschedule t instruction can timeslice table 11 instruction features
c o n f i d e n t i a l 4 instruction set STI5518 38/294 7170179 d 4.3 instruction-set tables function code memory code mnemonic processor cycles name notes 00xj 5jump d, t 1 1x ldlp 1 load local pointer 2 2x pfix 0 to 1 prefix 3 3x ldnl 2 load non-local 4 4x ldc 1 load constant 5 5x ldnlp 1 load non-local pointer 6 6x nfix 0 to 1 negative prefix 7 7x ldl 1 load local 8 8x adc 1 add constant o 99xcall8call a ax cj 1 or 5 conditional jump b bx ajw 2 adjust workspace c cx eqc 1 equals constant d dx stl 1 store local e ex stnl 2 store non-local f fx opr 0 operate table 12 primary functions memory code mnemonic processor cycles name notes 22fa testpranal 2 test processor analyzing 23fe saveh 3 save high priority queue registers 23fd savel 3 save low priority queue registers 21f8 sthf 1 store high priority front pointer 25f0 sthb 1 store high priority back pointer 21fc stlf 1 store low priority front pointer 21f7 stlb 1 store low priority back pointer 25f4 sttimer 2 store timer 2127fc lddevid 1 load device identity 27fe ldmemstartval 1 load value of memstart address table 13 processor initialization operation codes
c o n f i d e n t i a l STI5518 4 instruction set 7170179 d 39/294 memory code mnemonic processor cycles name notes 24f6 and 1 and 24fb or 1 or 23f3 xor 1 exclusive or 23f2 not 1 bitwise not 24f1 shl 1 shift left 24f0 shr 1 shift right f5 add 1 add a, o fc sub 1 subtract a, o 25f3 mul 4 multiply a, o 27f2 fmul 6 fractional multiply a, o 22fc div 5 to 37 divide a, o 21ff rem 5 to 40 remainder a, o f9 gt 1 greater than a 25ff gtu 1 greater than unsigned a f4 diff 1 difference 25f2 sum 1 sum f8 prod 4 product a 26f8 satadd 2 saturating add a 26f9 satsub 2 saturating subtract a 26fa satmul 5 saturating multiply a table 14 arithmetic/logical operation codes memory code mnemonic processor cycles name notes 21f6 ladd 2 long add a, o 23f8 lsub 2 long subtract a, o 23f7 lsum 2 long sum 24ff ldiff 2 long diff 23f1 lmul 5 to 6 long multiply a 21fa ldiv 5 to 39 long divide a, o 23f6 lshl 2 long shift left a 23f5 lshr 2 long shift right a 21f9 norm 2 to 5 normalize a 26f4 slmul 5 signed long multiply a, o 26f5 sulmul 5 signed times unsigned long multiply a, o table 15 long arithmetic operation codes
c o n f i d e n t i a l 4 instruction set STI5518 40/294 7170179 d memory code mnemonic processor cycles name notes f0 rev 1 reverse 23fa xword 4 extend to word a 25f6 cword 3 check word a, e 21fd xdble 2 extend to double 24fc csngl 3 check single a, e 24f2 mint 1 minimum integer 25fa dup 1 duplicate top of stack 27f9 pop 1 pop processor stack 68fd reboot 1 reboot table 16 general operation codes memory code mnemonic processor cycles name notes f2 bsub 1 byte subscript fa wsub 1 word subscript 28f1 wsubdb 1 form double word subscript 23f4 bcnt 1 byte count 23ff wcnt 1 word count f1 lb 1 load byte 23fb sb 2 store byte 24fa move move message i table 17 indexing/array operation codes memory code mnemonic processor cycles name notes 22f2 ldtimer 1 load timer 22fb tin timer input i 24fe talt 3 timer alt start 25f1 taltwt timer alt wait d, i 24f7 enbt 2 to 8 enable timer 22fe dist disable timer i table 18 timer handling operation codes
c o n f i d e n t i a l STI5518 4 instruction set 7170179 d 41/294 memory code mnemonic processor cycles name notes f7 in input message d fb out output message d ff outword output word d fe outbyte output byte d 24f3 alt 2 alt start 24f4 altwt 4 to 7 alt wait d 24f5 altend 9 alt end 24f9 enbs 1 to 2 enable skip 23f0 diss 1 disable skip 21f2 resetch 3 reset channel 24f8 enbc 2 to 5 enable channel 22ff disc 2 to 7 disable channel table 19 input and output operation codes memory code mnemonic processor cycles name notes 22f0 ret 3 return 21fb ldpi 1 load pointer to instruction 23fc gajw 3 general adjust workspace f6 gcall 6 general call 22f1 lend 5 to 8 loop end t table 20 control operation codes memory code mnemonic processor cycles name notes fd startp 5 start process f3 endp 4 to 6 end process d 23f9 runp 3 run process 21f5 stopp 2 stop process 21fe ldpri 1 load current priority table 21 scheduling operation codes
c o n f i d e n t i a l 4 instruction set STI5518 42/294 7170179 d memory code mnemonic processor cycles name notes 21f3 csub0 2 check subscript from 0 a, e 24fd ccnt1 3 check count from 1 a, e 22f9 testerr 2 test error false and clear 21f0 seterr 2 set error 25f5 stoperr 2 to 3 stop on error (no error) d 25f7 clrhalterr 1 clear halt-on-error 25f8 sethalterr 1 set halt-on-error 25f9 testhalterr 2 test halt-on-error table 22 error handling operation codes memory code mnemonic processor cycles name notes 25fb move2dinit 3 initialize data for 2d block move 25fc move2dall 2d block copy i 25fd move2dnonzero 2d block copy non-zero bytes i 25fe move2dzero 2d block copy zero bytes i table 23 2d block move operation codes memory code mnemonic processor cycles name notes 27f4 crcword 36 calculate crc on word a 27f5 crcbyte 12 calculate crc on byte a 27f6 bitcnt 3 count bits set in word a 27f7 bitrevword 2 reverse bits in word 27f8 bitrevnbits 2 reverse bottom n bits in word a table 24 crc and bit operation codes memory code mnemonic processor cycles name notes 27f3 cflerr 3 check floating point error e 29fc fptesterr 1 load value true (fpu not present) 26f3 unpacksn 10 unpack single length floating point num- ber a 26fd roundsn 7 round single length floating point number a 26fc postnormsn 9 post-normalize correction of single length floating point number a 27f1 ldinf 1 load single length infinity table 25 floating point support operation codes
c o n f i d e n t i a l STI5518 4 instruction set 7170179 d 43/294 memory code mnemonic processor cycles name notes 2cf7 cir 3 check in range a, e 2cfc ciru 3 check in range unsigned a, e 2bfa cb 3 check byte a, e 2bfb cbu 2 check byte unsigned a, e 2ffa cs 3 check sixteen a, e 2ffb csu 2 check sixteen unsigned a, e 2ff8 xsword 3 sign extend sixteen to word a 2bf8 xbword 3 sign extend byte to word a table 26 range checking and conversion instructions memory code mnemonic processor cycles name notes 2cf1 ssub 1 sixteen subscript 2cfa ls 1 load sixteen 2cf8 ss 2 store sixteen 2bf9 lbx 1 load byte and sign extend 2ff9 lsx 1 load sixteen and sign extend table 27 ndexing/array instructions memory code mnemonic processor cycles name notes 2ff0 devlb 3 device load byte a 2ff2 devls 3 device load sixteen a 2ff4 devlw 3 device load word a 62f4 devmove device move i 2ff1 devsb 3 device store byte a 2ff3 devss 3 device store sixteen a 2ff5 devsw 3 device store word a table 28 device access instructions memory code mnemonic processor cycles name notes 60f5 wait 5 to 11 wait d 60f4 signal 7 to 12 signal table 29 semaphore instructions
c o n f i d e n t i a l 4 instruction set STI5518 44/294 7170179 d memory code mnemonic processor cycles name notes 60f0 swapqueue 4 swap scheduler queue 60f1 swaptimer 5 swap timer queue 60f2 insertqueue 3 to 4 insert at front of scheduler queue 60f3 timeslice 3 to 4 timeslice 60fc ldshadow 6 to 31 load shadow registers a 60fd stshadow 6 to 17 store shadow registers a 62fe restart 20 restart 62ff causeerror 7 to 8 cause error 61ff iret 3 to 11 interrupt return 2bf0 settimeslice 2 set timeslicing status 2cf4 intdis 2 interrupt disable 2cf5 intenb 2 interrupt enable 2cfd gintdis 5 global interrupt disable 2cfe gintenb 5 global interrupt enable table 30 scheduling support instructions memory code mnemonic processor cycles name notes 26fe ldtraph 12 load trap handler l 2cf6 ldtrapped 12 load trapped process status l 2cfb sttrapped 12 store trapped process status s 26ff sttraph 12 store trap handler s 60f7 trapenb 4 trap enable 60f6 trapdis 4 trap disable 60fb tret 8 to 10 trap return table 31 trap handler instructions memory code mnemonic processor cycles name notes 68fc ldprodid 1 load product identity 63f0 nop 1 no operation table 32 processor initialization and no operation instructions memory code mnemonic processor cycles name notes 64ff clockenb 2 clock enable 64fe clockdis 2 clock disable 64fd ldclock 2 load clock 64fc stclock 2 store clock table 33 clock instructions
c o n f i d e n t i a l STI5518 5 interrupt system 7170179 d 45/294 5 interrupt system 5.1 introduction the interrupt system allows an on-chip module or external interrupt pin to interrupt an active process so that an interrupt handling process can be run. interrupts are signalled by one of the following: a signal on an external interrupt pin; a signal from an internal peripheral or subsystem; software asserting an interrupt in the pending register. interrupts are implemented by an on-chip interrupt controller and an on-chip interrupt level controller . the interrupt level controller multiplexes the 31 incoming interrupt sources onto the eight programmable interrupt level inputs of the interrupt controller. this multiplexing is controlled by software. this is illustrated in the figure below. 5.2 interrupt controller the interrupt controller supports eight prioritized interrupts as inputs, and manages the pending interrupts. this allows nested pre-emptive interrupts for real-time system design. interrupt level 7 has the highest priority and interrupt level 0 has the lowest priority. all interrupts are at a higher priority than the low-priority process queue. each interrupt can be programmed to be at a lower or higher priority than the high-priority process queue by writing to the priority bit in the inc_handlerwptr registers. interrupts which are specified as higher priority must be contiguous from the highest numbered interrupt downwards. for example, if 4 interrupts are programmed as high-priority and 4 as low-priority, then the higher priority interrupts must be set to interrupt7:4 and the lower priority interrupts to interrupt3:0. each of the eight interrupt levels of the interrupt controller can be programmed with a interrupt trigger mode, using the inc_triggermode register. the trigger mode can be set to be high or low level, or rising edge, falling edge or any edge sensitive. note that all on-chip module interrupt sources produce active-high level interrupt signals. therefore the figure 8 STI5518 interrupt system cpu interrupt controller interrupt level controller 8 prioritized interrupt levels n interrupt sources (where n is 0-30) on-chip module n=2 on-chip module n=1 on-chip module n=23 on-chip module n=22 on-chip module n=0 irq0 pin 127 - servo interrupt request (n=24) irq1 pin 126 - atapi interrupt request (n=25) irq2 pin 125 - md interrupt request (n=26) audio interrupt from mpegav block (n=27) video interrupt from mpegav block (n=28) ac3 interrupt from mpegav block (n=29) link interface interrupt (n=30)
c o n f i d e n t i a l 5 interrupt system STI5518 46/294 7170179 d interrupt level that these interrupt sources are multiplexed onto (by the interrupt level controller) must be programmed with a high-level trigger mode. furthermore, each of the eight interrupt levels can be programmed to be enabled or disabled by the inc_mask register. the default state of inc_mask is that all interrupt levels are disabled. a corresponding level bit is set in the inc_pending register if the interrupt signal from the interrupt level controller matches the level trigger condition. if this is the highest priority bit set in the inc_pending register, the cpu will then execute the interrupt handler associated with that level by the inc_handlerwptr register and the inc_pending bit will then be reset. if the level bit set in the inc_pending register is not the highest priority bit set, then the bit remains set until it is the highest priority level bit, then the cpu executes the associated interrupt handler for that level. note the cpu will only execute the interrupt handler and then clear the inc_pending register bit if it is enabled in the inc_m ask register. software can write to the inc_pending register to generate a software interrupt on any of the eight interrupt-levels. programming of the inc_mask, inc_pending and inc_triggermode registers is supported via the operating system run time library functions of stlite (a.k.a os20). the interrupt controller also contains an inc_exec register used by the interrupt controller logic to keep a record of which interrupt-level handler is currently executing on the cpu (or was previously executing before being pre-empted by a high priority process, for low priority interrupts) and which levels have been pre-empted by higher priority interrupt levels. this register can be read by user software, if required, but the register must never be written to as its behavior is undefined. 5.3 interrupt vector table the interrupt controller contains a table of pointers to interrupt handlers. there are 8 interrupt handlers, each controlled by a work-space register inc_handlerwptr 0-7. the table of pointer values contains a work-space pointer for each interrupt level. the inc_handlerwptr registers access the code, data and interrupt-save area of the interrupt handler. the position of the inc_handlerwptr register in the interrupt table sets the priority of the interrupt. the operating system run time library (stlite a.k.a. os20) supports the setting and programming of the vector table. figure 9 interrupt priority interrupt 7 interrupt 0 high priority low priority increasing pre-emption . . . . process process interrupt 7 interrupt 0 . . . . when priority bit set to 1 when priority bit set to 1 when priority bit set to 0 when priority bit set to 0
c o n f i d e n t i a l STI5518 5 interrupt system 7170179 d 47/294 5.4 interrupt handlers at any interruptible point in its execution, the cpu can receive an interrupt request from the interrupt controller. the cpu immediately acknowledges the request. in response to receiving an interrupt, the cpu performs a procedure call to the process in the vector table. the state of the interrupted process is stored in the work space of the interrupt handler as shown in figure 10 . each interrupt level has its own work space. the interrupt routine is initialized with space below handlerwptr . the iptr and status word for the routine are stored there permanently. this should be programmed before the handlerwptr is written into the vector table. the behavior of the interrupt differs depending on the priority of the cpu when the interrupt occurs. if an interrupt occurs when the cpu is running at high priority, and the interrupt is set at a higher priority than the high priority process queue, the cpu saves the current process state (areg, breg, creg, wptr, iptr and status) into the workspace of the interrupt handler. the value handlerwptr , which is stored in the interrupt controller, points to the top of this work space. the values of iptr and status to be used by the interrupt handler are loaded from this work space and starts executing the handler. the value of wptr is then set to the bottom of this save area. if an interrupt occurs when the cpu is running at high priority, and the interrupt is set at a lower priority than the high priority process queue, no action is taken and the interrupt waits in a queue until the high priority process queue is empty (see pre-emption and interrupt priority on page 48 ). interrupts always take priority over low priority processes. if an interrupt occurs when the cpu is idle or running at low priority, the status is saved. this indicates that no valid process is running ( null status ). the interrupted processes (low priority process) state is stored in shadow registers. this state can be accessed via the ldshadow (load shadow registers) and stshadow (store shadow registers) instructions. the interrupt handler is then run at high priority. when the interrupt routine has completed it must adjust wptr to the value at the start of the handler code and then execute the iret (interrupt return) instruction. this restores the interrupted state from the interrupt handler structure and signals to the interrupt controller that the interrupt has completed. the processor will then continue from where it was before being interrupted. figure 10 state of interrupted process before interrupt handlerwptr areg breg creg interrupting high priority handlerwptr wptr iptr status handlerwptr null status process interrupting low priority process or cpu idle handler iptr handler status handler iptr handler status handler iptr handler status
c o n f i d e n t i a l 5 interrupt system STI5518 48/294 7170179 d 5.5 interrupt latency the interrupt latency depends on the type of data being accessed, and the position in memory of the interrupt handler and the interrupted process. this allows a trade-off of between fast internal sram memory and interrupt latency. 5.6 pre-emption and interrupt priority each interrupt channel has an implied priority fixed by its place in the interrupt vector table. all interrupts cause scheduled processes of any priority to be suspended and the interrupt handler started. once an interrupt has been sent from the controller to the cpu the controller keeps a record of the current executing interrupt priority in the inc_exec register. this is only cleared when the interrupt handler executes a return from interrupt ( iret ) instruction. interrupts of a lower priority arriving are blocked by the interrupt controller until the interrupt priority is low enough for the routine to execute. an interrupt of a higher priority than the currently executing handler is passed to the cpu and causes the current handler to be suspended until the higher priority interrupt is serviced. in this way, interrupts can be nested and a higher priority interrupt always pre-empts a lower priority one. note: deep nesting and the placing of frequent interrupts at high priority can result in systems where low priority interrupts are never serviced or cpu time is consumed in nesting interrupt priorities instead of executing the interrupt handlers. 5.7 restrictions on interrupt handlers for optimum interrupt handling, the following restrictions are placed on interrupt handlers: interrupt handlers must not deschedule. interrupt handlers must not execute communication instructions. however they may communicate with other processes through shared variables using the semaphore signal to synchronize. interrupt handlers must not perform cpu 2d block move instructions. interrupt handlers must not cause program traps. however they may be trapped by a scheduler trap.
c o n f i d e n t i a l STI5518 5 interrupt system 7170179 d 49/294 5.8 interrupt level controller the interrupt level controller multiplexes 31 incoming interrupt source signals onto the eight interrupt level inputs of the interrupt controller. in this way, it gives programmable control of the priority of the interrupt sources and extends the number of possible interrupts to 31. the incoming interrupt signals can be generated by on-chip subsystems or received from external pins. table 34 on page 50 assigns each of the interrupt sources to a number n from 0-30. software assigns a signal n to one of the 8 interrupt levels by writing the priority of the required input in the register inc_intnpriority. each of the 31 interrupt sources in the interrupt level controller can be selectively enabled or disabled at source, by writing to the inc_src_mask register. this is in addition to the individual masking of the 8 levels in the interrupt controller. this means that the user can disable just the interrupt source from generating an interrupt, without disabling all other interrupt sources mapped onto that interrupt level. this would be the case if the inc_mask register in the interrupt controller was used. each interrupt source can be used to trigger an interrupt and can be programmed to trigger on rising or falling edges, or on the high or low logic level of the incoming interrupt source signal. this is controlled by writing to the inc_src_triggermode registers. the STI5518 enhanced feature interrupt level controller is software backward compatible with the interrupt level controller in the sti5500, sti5505 and sti5508. backward compatibility can be maintained by setting the interrupt trigger on the interrupt levels in the interrupt controller, as was done before. the default state of the interrupt level controller trigger mode registers is high, therefore, these new registers do not need to be programmed. in this case the interrupt level controller will effectively pass the interrupt source signal through, unmodified, to the interrupt controller . the default state of all of the inc_src_mask register bits is 1, meaning that all of the interrupt sources are enabled. this is again to maintain software backwards compatibility. if the non-default trigger modes in the interrupt level controller are to be used, the corresponding trigger mode for the interrupt level in the interrupt controller that the source(s) are mapped to, must be programmed to high level. otherwise, the trigger mode in the interrupt controller and the interrupt level controller may conflict. the inc_inputinterrupt register has the same function as before in sti5500, sti5505, sti5508 and can be used to indicate the current logic state of the all the interrupt sources. note that this register is just a buffered version of the interrupt source signals before the trigger mode detection stage and does not latch the signal, as does the inc_src_status register, for interrupt sources defined with an edge sensitive trigger mode. the inc_src_status register is more useful, because of this feature, as it can be read by the interrupt handler software routine to determine which interrupt sources have triggered. for example, if the interrupt source is external and provides a pulse, the interrupt level controller would have the interrupt source trigger mode set to be rising edge. on a rising edge the corresponding bit in the inc_src_status register would be set high and would remain set until explicitly cleared by the interrupt handler routine writing to the corresponding bit in the inc_src_clear register. however if the pulse was short, by the time the interrupt handler was executed and it read the inc_inputinterrupt register, the pulse may have returned to a logic low and the bit would be read as zero. thus the cause of interrupt could not be determined if more than one interrupt source had been multiplexed onto the interrupt level. so now, using the inc_src_status register, it is possible to multiplex interrupt sources of different types, including edge sensitive, onto the same interrupt level in the interrupt controller. the STI5518 interrupt level controller also has two new registers mapped into its register address space, that have no connection with normal interrupt operation. these registers are for controlling waking up the cpu by an external interrupt pin, when it has been put into low power mode, by the low power controller module. the register inc_selnotinv controls whether the three external interrupt pins are active high or low, to wake up the cpu from low power mode. note that the setting of this register has no effect on the triggering of the external interrupt pins in the interrupt level controller. the register inc_en_int is a mask register to enable or disable the external interrupt pins from waking up the cpu from low power mode. again, this has no effect on the masking of these interrupts in the interrupt level controller.
c o n f i d e n t i a l 5 interrupt system STI5518 50/294 7170179 d 5.9 interrupt assignments all interrupts are active high. interrupts from the internal peripherals and external pins are assigned as in the table below. int n peripheral description of the functions 0 pio 0 compare function 1 pio 1 compare function 2 pio 2 compare function 3 pio 3 compare function 4 pio 4 compare function 5 ssc0 ssc0tir, ssc0rir, ssc0eir i 2 c master 6 ssc1 ssc1tir, ssc1rir, ssc1eir i 2 c master 7 uart 3 asc3tir, asc3tbir, asc3rir, asc3eir 8 uart 2 asc2tir, asc2tbir, asc2rir, asc2eir 9 uart 1 asc1tir, asc1tbir, asc1rir, asc1eir 10 uart 0 asc0tir, asc0tbir, asc0rir, asc0eir 11 pwm and capture pwmfunctions, (capture0int, capture1int tbd) 12 mpeg3dma 0 mpeg3dma0 interrupt 13 mpeg3dma 1 mpeg3dma1 interrupt 14 mpeg3dma 2 mpeg3dma 2 inside the link interface interrupt 15 block move blockmove interrupt 16 modem dma mafe modem interface interrupt 17 pio5 compare function 18 ir blaster tx, rx interrupts 19 teletext ttxt dma interrupt 20-23 reserved tied low internally 24 irq0 pin 127 servo interrupt request 25 irq1 pin 126 atapi interrupt request 26 irq2 pin 125 md interrupt request 27 mpegav block audio interrupt from mpegav block 28 mpegav block video interrupt from mpegav block 29 mpegav block sector processor interrupt or hdd link interrupt 30 link interface interrupt link interface interrupt table 34 STI5518 interrupt assignments
c o n f i d e n t i a l STI5518 6 memory map 7170179 d 51/294 6memory map 6.1 overview the STI5518 has a 32-bit signed 2s-complement address space. a byte of memory is addressed by a 30-bit word address plus a 2-bit byte-selector identifier in the word. a word of memory is addressed by a 30-bit word address with the byte-selector set to zero. memory is divided into areas with different purposes. some areas are dedicated to a specific purpose, either because they contain memory-mapped devices or because they are reserved by the system. the figure below shows the memory map. figure 11 memory map 4 kbyte sram 2 kbyte configurable as data cache or sram 0x80001800 0xc0000000 0x00000000 0x80000000 0x80001000 shared sdram 0xc0800000 0x40000000 emi bank 0 emi bank 1 emi bank 2 emi bank 3 0x50000000 0x60000000 0x70000000 peripheral configuration registers 0x20040000 region 0 region 3 region 2 region 1 not available reserved not available 0xffffffff
c o n f i d e n t i a l 6 memory map STI5518 52/294 7170179 d memory is normally accessed by the load , store , block move and channel instructions. these will use data cache if it is enabled, and do not guarantee the order of accesses to different addresses. 6.2 mapping the address space is divided into the following regions: region 0: dcache or sram, the bottom 4 kbytes (or 6 kbytes if the data cache is not used) is occupied by on-chip sram. region 1: shared sdram, the 8 mbyte area from 0xc0000000 to 0xc07fffff is for sdram and is shared with the mpeg decoders; region 2: peripheral configuration registers, the area from 0x00000000 to 0x3fffffff is dedicated to memory- mapped or command-mapped on-chip peripherals; region 3: emi banks0 to 3, 0x40000000 to 0x7fffffff is for external memory and peripherals, accessed through the emi designation start end description mpeg #00000000 #000001ff mpeg video #00000200 #000002ff mpeg audio #00000400 #000005ff sub-picture decoder #00000600 #000006ff denc decoder #00000700 #000007ff reserved #00000800 #000009ff mpeg video fifos accesses #00000a00 #00000bff mpeg audio fifos accesses #00000c00 #00000dff sub-picture decoder accesses #00000e00 #00000fff mpeg control registers configuration #00002000 #00002fff emi configuration #00003000 #00003fff dcu #00004000 #00004fff cache configuration #00005000 #1fffffff reserved table 35 STI5518 memory map
c o n f i d e n t i a l STI5518 6 memory map 7170179 d 53/294 peripherals #20000000 #20000fff int. controller #20003000 #20003fff uart0 (asc0) smartcard 0 #20004000 #20004fff uart1 (asc1) #20005000 #20005fff uart2 (asc2) #20006000 #20006fff uart3 (asc3) smartcard 1 #20007000 #20007fff sccg0 (smcard 0 clkgen ) #20008000 #20008fff sccg1 (smcard1 clkgen) #20009000 #20009fff ssc0 #2000a000 #2000a0ff ssc1 #2000a100 #2000a1ff pio5 #2000a200 #2000a2ff ir blaster #2000a300 #2000a3ff ttxt #2000a400 #2000afff reserved #2000b000 #2000bfff pwm #2000c000 #2000cfff pio 0 #2000d000 #2000dfff pio 1 #2000e000 #2000efff pio 2 #2000f000 #2000ffff pio 3 #20010000 #20010fff pio 4 #20011000 #20011fff ilc #20024000 #20024fff mpegdma 0 #20025000 #20025fff mpegdma 1 #20026000 #20026fff block move dma #20027000 #20027fff modem dma #20030000 #20037fff reserved #20038000 #2003ffff link extra (link interface) designation start end description table 35 STI5518 memory map
c o n f i d e n t i a l 6 memory map STI5518 54/294 7170179 d region 3 emi banks0 to 3 0x40000000 0x4fffffff emi bank 0. sdram/dram supported 0x50000000 0x5fffffff emi bank 1. sdram/dram supported 0x60000000 0x6fffffff emi bank 2. sdram/dram not supported 0x70000000 0x7fffffff emi bank 3, normally used for boot rom. dram not sup- ported 0x7ffffffe boot entry point region 0 dcache or sram 0x80000000 0x80000003 reserved 0x80000004 0x8000000f reserved 0x80000010 0x80000013 reserved 0x80000014 0x8000003f reserved 0x80000040 0x8000004f high priority breakpoint trap handler 0x80000050 0x8000005f high priority breakpoint trapped process 0x80000060 0x8000006f high priority error trap handler 0x80000070 0x8000007f high priority error trapped process 0x80000080 0x8000008f high priority systemoperations trap handler 0x80000090 0x8000009f high priority systemoperations trapped process 0x800000a0 0x800000af high priority scheduler trap handler 0x800000b0 0x800000bf high priority scheduler trapped process 0x800000c0 0x800000cf low priority breakpoint trap handler 0x800000d0 0x800000df low priority breakpoint trapped process 0x800000e0 0x800000ef low priority error trap handler 0x800000f0 0x800000ff low priority error trapped process 0x80000100 0x8000010f low priority systemoperations trap handler 0x80000110 0x8000011f low priority systemoperations trapped process 0x80000120 0x8000012f low priority scheduler trap handler 0x80000130 0x8000013f low priority scheduler trapped process 0x80000140 0x80000fff internal sram: < 4 kbytes user code, data and stack 0x80001000 0x800017ff internal sram if data cache is not enabled.user-code, data and stack 0x80001800 0xbfffffff reserved region 1 shared sdram 0xc0000000 0xc07fffff sdram. video memory, user code, data, stack 0xc0400000 0xffffffff reserved designation start end description table 35 STI5518 memory map
c o n f i d e n t i a l STI5518 6 memory map 7170179 d 55/294 6.3 system memory use the following sections of address space are reserved for system use: the locations below the address memstart at the bottom of memory are dedicated to processor use. the address of memstart is returned by the ldmemstartval instruction. when booting from rom, the system boots from the predefined location bootentry (0x7ffffffe) at the top of memory. areas of memory reserved for processor use should not be accessed directly. special instructions are provided for manipulating these areas. the special address memstart marks the base of user memory space. peek and poke use the two words above memstart , i.e. memory locations 0x80000140 to 0x80000147. the use of peek and poke is described in system services on page 82 . subsystem channels memory each channel based dma subsystem is allocated a word of storage below memstart . this is used by the processor to store information about the state of that channel. this information should not normally be examined directly, although debugging kernels may need to do so. interrupting dma subsystems do not have a channel word allocated and rely on interrupts to perform synchronization with the processes running on the processor. memory for trap handlers the area of memory reserved for trap handlers is broken down hierarchically as follows: each high/low process priority has a set of trap handlers; each set of trap handlers has a handler for each of the four trap groups; each trap group handler has a trap handler structure and a trapped process structure; each of the structures contains four words. the contents of these addresses can be accessed via ldtraph , sttraph , ldtrapped and sttrapped instructions. boot rom when the processor boots from rom, it jumps to a boot program held in rom with an entry point 2 bytes from the top of memory at 0x7ffffffe. these 2 bytes are used to encode a negative jump of up to 256 bytes down in the rom program. for large rom programs it may then be necessary to encode a longer negative jump to reach the start of the routine.
c o n f i d e n t i a l 7 memory STI5518 56/294 7170179 d 7memory 7.1 external memory programmable cpu interface memory the programmable cpu interface memory (commonly referred to as the emi) decodes region 3 of the address space into four banks, into which different external memories and peripherals can be mapped. further details of the emi can be found in programmable cpu memory interface on page 63 . two of the banks support dram and one bank is normally used for boot rom. locations 0x40000000 to 0x5fffffff (banks 0 and 1) are generally used for sdram/dram, but may be used for any external memory or peripherals. the locations 0x60000000 to 0x6fffffff (bank 2) may be used for any external memory or peripherals except sdram/dram. the locations 0x70000000 to 0x7fffffff (bank 3) may be used for any external memory or peripherals except sdram/dram, but are generally used for boot rom. when booting from rom, the system boots from the predefined location bootentry (0x7ffffffe) at the top of memory space. accessing some areas of memory causes special access characteristics (strobes etc.) to be generated depending on the way the emi is programmed. the emi provides address decoding, address and data buses, timing strobes, enabling signals and refresh where appropriate. shared sdram memory the shared sdram memory occupies the first 16, 32 or 64 mbits of region 1, and is shared with the mpeg decoders. osd bitmaps, for example, are stored in this memory. for details of the shared sdram memory interface configuration and set-up, refer to the register manual. 7.2 on-chip sram memory this internal memory module, known as on-chip memory, contains 6 kbytes of sram, which is mapped into the lowest 6 kbytes of memory space from minint (0x80000000) extending upwards, as shown in figure 11 on page 51 . part of the lowest 4 kbytes of memory is committed to system use; see system memory use on page 55 for details. the remainder of the lowest 4 kbytes of memory is uncommitted and can be used to store on-chip data, stack or code for time-critical routines. the upper 2 kbytes of the on-chip memory is also uncommitted sram, and is contiguous with the lower 4 kbytes. however, it can be configured to be the data cache, as described below, in which case it is not available as sram. locations between 0x80001800 (or 0x80001000 if data cache is used) and 0xbfffffff should not be addressed. 7.3 caching cache can be used to reduce the average access delay imposed on the cpu when it accesses a memory location to read or write. some locations should not be cached, for example those to which other modules have direct memory access ( dma) and the cpu also requires access to those locations. this is because dma operations always bypass the data cache and so cache incoherence problems will occur. it is therefore recommended to configure such memory locations as being non-cacheable. the STI5518 cache subsystem provides:
c o n f i d e n t i a l STI5518 7 memory 7170179 d 57/294 2 kbytes of direct-mapped write-back data cache 2 kbytes of direct-mapped read-only instruction cache the cache configuration is held in memory-mapped registers. the registers must be accessed using the device access instructions. device access instructions can also be used to force access to external memory as they bypass the cache. device writes do not change the value in the cache. these instructions can be used to solve any cache coherency issues, for example where data is being dma copied from a cached location. however care must be taken in using device access instructions to access memory (rather than device registers) as cache coherency problems may occur rather than being solved, if the cpu also performs normal (therefore cached) memory accesses to these locations. registers are provided to configure areas of memory to be cacheable or non-cacheable for data access, as described in cacheable and non-cacheable memory locations on page 60 . note that the correct cache initialization sequences, described in cache initialization on page 58 , must be used before the caches are enabled. 7.3.1 outline of operation the cache is four 32-bit words (16 bytes) wide and 128 lines (2 kbytes, 512 words) high. it is direct-mapped (sometimes called one way set associative ). this is shown in figure 12 below. each line of the cache can only store data from specific four-word sections of memory at 2 kbyte intervals, with the bottom line of the cache coinciding with the 4 words just above each 2 kbyte boundary. thus the line number of the cache pinpoints the four-word section of memory within a 2 kbyte block, i.e. bits 4 to 10 of the address. the 21 most significant bits of the address selects the 2 kbyte block. these 21 bits are stored in 128 tag registers, with one tag figure 12 kbyte data or instruction cache2 16 bytes per line 128 lines address tag bits 31 to 11
c o n f i d e n t i a l 7 memory STI5518 58/294 7170179 d register corresponding to each cache lines. the significance of the parts of the address when using the cache are shown in the figure below. if a request is made to access a cacheable memory location, and a copy of that location is held in cache, then the access is said to have made a cache hit. a hit is identified by comparing the address bits 11 to 31 with the address tag for the cache line given by the address bits 4 to 10. if the cache is hit, then the access is completed by the cache subsystem. if the cache is missed, the appropriate cache line is written back to memory, and if necessary the new location in memory is read into that cache line. all cache reads and writes to memory are complete lines because of the efficiency of accessing the memory in burst mode. 7.3.2 cache initialization before the caches are enabled, they must be correctly initialized. to do this the cache must first be invalidated before it is accessed. to ensure this occurs, the invalidate bit of each cache must be set with the cache disabled and then the enable bit set to enable the cache. this sequence has the effect of forcing a cache to be invalid, which initializes the cache state before any other accesses are considered by the cache. 7.3.3 cache subsystem control the cache subsystem registers control cache functions such as flushing and invalidation, and are used to mark sections of memory space as cacheable or not cacheable. registers should be accessed using the device access instructions. the cac_cachecontrollock must be 0 before some registers can be changed. after changing registers, the cac_cachecontrollock should be set to 1. once this lock is set it cannot be cleared except by a reset. it is not recommended to change the cache configuration other than at reset. 7.3.4 data cache it is possible to select either data cache or an extra 2 kbyte of on-chip sram. this is done by writing to the cac_dcachenotsram register. the default is to enable the extra on-chip sram. set the cac_dcachenotsram bit to 1 to select data cache mode and enable the cache. do not access locations 0x80001000 to 0x800017ff when using the data cache. the cache invalidate bit should be set before enabling the cache. invalidating a cache marks every line as not containing valid data. this is done by setting the cac_invalidatedcache register to 1. this register is automatically reset to 0 on completion of the task, but it cannot be directly read by the cpu as the register is write only. therefore bit 2 is provided in the cac_cachestatus register to indicate when the invalidate operation has completed. figure 13 address fields when using cache 4-bit selector of byte within cache line 0 3 4 10 31 7-bit selector of line in 2 kbyte memory block or cache 21-bit address tag
c o n f i d e n t i a l STI5518 7 memory 7170179 d 59/294 note that for the data cache, setting the cac_invalidatedcache register before the cache is enabled does not actually cause the invalidation sequence to begin. this only occurs when the cache is enabled when writing to the cac_dcachenotsram register. so the initialize sequence of operations should be: write 1 to the cac_invalidatedcache register; write 1 to the cac_dcachenotsram register as an ? atomic ? operation. where, ? atomic ? means than no other cpu software processes / tasks, trap handlers or interrupt handlers can execute in the time between the write to invalidate register and the write to cache enable register. note: this will normally be the case as the cache initialization should be performed during the initialization stage of the application code, before any operating system (stlite/os20) or interrupt handlers have been installed. wait for the invalidate sequence ( 128 cpu clock cycles) to finish. this can done by a software delay loop and/ or by polling bit 2 of the cache status register. note it is recommended to ensure that the cpu does not attempt to execute any code or access any data in cacheable memory locations before the invalidate sequence has finished. therefore if the cache initialization is done by the cpu (rather than by poking the registers via the tap and dcu, before booting the application code from the software toolset) the cpu software (code and data) that waits for the invalidate sequence to finish should reside in non- cacheable memory locations, so that the cache is not accessed while it is still invalidating. if this is not ensured it is possible for data corruption to occur. it is not recommended to change selection from data cache to sram during operation. however, if it is necessary to do so, it is essential to flush the cache to maintain memory integrity before making the change. flushing the cache means forcing a write-back to memory of every dirty line in the cache. a dirty line is a line of cache that has been written to since it was loaded or last written back. only the data cache can be flushed; the instruction cache never needs flushing since it is read only. to flush the data cache, set the cac_flushingdcache register to 1. it is automatically reset to 0 on completion of the task, but cannot be read directly by the cpu as the register is write only. therefore to check that the flush operation has finished it is necessary to poll bit 4 of the cache status register. ensure that the cache-flush software function is ? atomic ? and operates as follows: writes to the flush register; waits for the flush to finish; writes to the cac_dcachenotsram register as an ? atomic ? operation. where, ? atomic ? means than no other software processes / tasks, trap handlers or interrupt handlers can execute in the time between writing to the flush register and the dcache being changed back to sram mode. note: the cpu code function and associated data used to perform this sequence must be placed in non-cacheable memory locations, so the cache is not accessed while it is still flushing. 7.3.5 instruction cache to use the instruction cache it must be first be invalidated by writing 1 to the cac_invalidateicache register. invalidating a cache marks every line as not containing valid data. this is done by setting the cac_invalidateicache register to 1. this register is automatically reset to 0 on completion of the task (128 cpu cycles). however this register can not be read by the cpu, as it is write only, therefore bit 3 ( invalidating icache) in the cac_cachestatus register can be read instead to check that the invalidate operation has completed. the instruction cache must be allowed to complete the invalidate operation before the cache is enabled. note: unlike the data cache the instruction cache actually starts the invalidation sequence when the cac_invalidateicache is written to and so can be allowed to complete before enabling the cache by writing to the cac_enableicache register.
c o n f i d e n t i a l 7 memory STI5518 60/294 7170179 d the instruction cache can then be enabled by writing 1 to the cac_enableicache register; the default condition is disabled, no instruction cache. the cac_cachestatus register is read only, and shows the current state of the caches. the cache configuration can be locked by writing a 1 to the cac_cachecontrollock register bit. reset of this flag is only performed by a hardware reset. this bit should be set to 1 after all the cache configuration registers have been written. 7.3.6 cacheable and non-cacheable memory locations note: the cacheability control registers for both region1 and region 3 should be programmed before the caches are enabled. in this way the cacheable and non-cacheable memory areas are already defined when the caches are enabled, see cache initialization on page 58 . do not dynamically change these registers after cache initialization. figure 14 memory cacheability map 0x80000000 0x40000000 0x7fffffff 4k sram 0x80001000 0x00000000 memory size is 1g byte 0xc0100000 0xc0800000 sdram 16*512kbyte blocks sdram 16*64kbyte blocks not available 0x70000000 0x60000000 0x50000000 0xc0000000 not available 0x80001800 not cacheable as data cache all cacheable as instruction cache 2kbytes dcache configurable as sram region 0 (internal sram) region 1 (shared memory interface) region 2 (peripheral registers) region 3 emi bank3 emi bank2 emi bank1 emi bank0 emi block0-7
c o n f i d e n t i a l STI5518 7 memory 7170179 d 61/294 region 0 region 0 is used only to access internal sram and is, therefore, never cacheable for either icache or dcache. there are always 4k of sram. because the dcache can be configured to be sram, there can be another 2k sram (for a total amount of 6k sram). this is controlled by the cac_dcachenotsram register, which must be configured to ? 0 ? for sram, or to ? 1 ? for dcache. region 1 this region is mostly non-cacheable for data access. it can be programmed to be cacheable (default is non-cacheable) in either 16 blocks of 64k bytes or 16 blocks of 512k bytes. these blocks are contiguous and are placed starting from the address 0xc0000000. each one of these blocks may be selected individually as cacheable or non-cacheable for dcache memory accesses. this is controlled by two cac registers (cac_cachecontrol0 and 1), where each bit controls the cacheability characteristics of a particular 64k/512k block. to select between 64k byte or 512k byte block size, bit 8 of cac_cachecontrol0 register is used. after reset, all blocks are marked non-cacheable and the size of each block is set to 64k byte. the registers must then be programmed to mark certain blocks cacheable. the remainder of region1 is non-cacheable for dcache. region 2 always non-cacheable for dcache, but is all cacheable for icache. figure 15 region1 cacheable area with block sizes of 64k byte and 512kbyte. 0xffff ffff 0xc000 0000 0xc010 0000 block 15 0xc00f 0000 block 14 0xc00e 0000 block 13 0xc00d 0000 block 12 0xc00c 0000 block 11 0xc00b 0000 block 10 0xc00a 0000 block 9 0xc009 0000 block 8 0xc008 0000 block 7 0xc007 0000 block 6 0xc006 0000 block 5 0xc005 0000 block 4 0xc004 0000 block 3 0xc003 0000 block 2 0xc002 0000 block 1 0xc001 0000 block 0 0xc000 0000 64 kbyte blocks 0xc00f ffff 0xffff ffff 0xc000 0000 0xc080 0000 block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 512 kbyte blocks 0xc07f ffff region 1 region 1 0xc078 0000 0xc070 0000 0xc068 0000 0xc060 0000 0xc058 0000 0xc050 0000 0xc048 0000 0xc040 0000 0xc038 0000 0xc030 0000 0xc028 0000 0xc020 0000 0xc018 0000 0xc010 0000 0xc008 0000 0xc000 0000
c o n f i d e n t i a l 7 memory STI5518 62/294 7170179 d region 3 this region is split into 4 emi banks, 0-3. for icache they are all cacheable. for dcache they can be set as cacheable or non-cacheable by the 4-bit register cac_cachecontrol3, the default is non-cacheable. emi bank 0 is split into two parts; the upper part is cacheable in the same way as emi banks 1-3 and the lower part, containing 8 x 64kbyte blocks, can be set non-cacheable. these blocks, located between 0x40000000 and 0x4007ffff, can be set cacheable by the 8-bit register cac_cachecontrol2. figure 16 region 3 0x40000000 0x50000000 0x5fffffff 0x60000000 0x6fffffff 0x70000000 0x7fffffff 0x4007ffff 0x4fffffff emi bank 3 emi bank 2 emi bank 1 emi bank 0 0x4008 0000 block 7 0x4007 0000 block 6 0x4006 0000 block 5 0x4005 0000 block 4 0x4004 0000 block 3 0x4003 0000 block 2 0x4002 0000 block 1 0x4001 0000 block 0 0x4000 0000 64 kbyte blocks
c o n f i d e n t i a l STI5518 8 programmable cpu memory interface 7170179 d 63/294 8 programmable cpu memory interface the programmable cpu interface (emi) controls the movement of data between the STI5518 and off-chip memory, except for the shared sdram which is connected to a dedicated interface (smi). the emi uses minimal external support logic to support memory subsystems. the emi accesses a 32 mbytes physical address space (greater if sdram or dram is used) in four general purpose memory banks of 8 or 16 bits wide, 21 or 22 address lines, and byte select. for dvd applications requiring extra memory, the emi supports this extra memory with zero external support logic. the interface can be configured for a wide variety of timing and decode functions through configuration registers. the emi maps external memory into the top quarter of the address space and is partitioned into four banks with each bank occupying one sixteenth of the total address space. systems can use several memory types such as sdram, dram, sram, flash eprom, and other peripherals. the figure below illustrates the programmable cpu interface memory allocation. warning! it is not possible to have sdram and dram on the programmable cpu interface at the same time. figure 17 memory allocation 00000000 7fffffff ffffffff 80000000 internal sram bfffffff c0000000 3fffffff 40000000 on-chip peripheral registers (including the emi and cache configuration registers) are mapped into this region. physical addresses on-chip peripheral registers emi bank0 emi bank1 emi bank3 emi bank2 70000000 60000000 50000000 80001000 80001800 sram (d-cache off)
c o n f i d e n t i a l 8 programmable cpu memory interface STI5518 64/294 7170179 d the timing of each of the four memory banks can be selected separately, with different device types being placed in each bank with no external hardware support. banks can be configured to contain 8-bit wide or 16-bit wide devices. the emi supports three memory types: sdram with a multiplexed row and column address; dram with a multiplexed row and column address used to support fast page mode; sram or peripherals, which is used to support srams, peripherals, eprom or flash roms. emi banks 0 and 1 support either memory type, while banks 2 and 3 only support sram or peripheral memory types. words of 1 byte and 2 bytes can be addressed. the behavior of some strobes depends on whether the bank being accessed has been configured as sdram, dram or sram / peripheral 8.1 pin functions note a cycle is defined as one processor clock cycle, and a phase as a half of one processor clock cycle. the table below describes the functions of the programmable cpu interface pins. note that a signal name prefixed by not indicates that the pin is active-low. the pins are listed in alphabetical order. pin function boot_from_ rom when the boot_from_rom pin is held low, the STI5518 boots from the dcu. when the boot_from_rom pin is held high, the STI5518 boots from rom. boot code is run from an external rom in bank 3 (at the top of memory). the boot_from_rom pin is also used to encode the size of bank3 (which is 16-bit), and this value overrides the portsize value in the bank 3 configuration registers. if the STI5518 is being booted by the dcu, then the bootstrap must execute from internal memory until the emi has been configured. cpu_addr[1:21] and [22] the address bus operates in both multiplexed and non-multiplexed modes. when a bank is configured to con- tain sdram, dram, or another multiplexed memory, the device type is set to sdram or dram, and the inter- nally generated 32-bit address is multiplexed as row and column addresses through the external address bus. an extra address bit cpu_addr[22] is used when no dram or sdram support is required on the program- mable cpu interface. this pin allows direct addressing of up to 8mbytes in peripheral sram modes. it is also used for the notcpu_cas[0] signal. cpu_data[0:15] the data bus transfers 16 or 8-bit data items depending on the bus width configuration. the least significant bit of the data bus is always cpu_data[0]. the most significant bit varies with bus width. it will be cpu_data15 for 16-bit data items, and cpu_data7 for 8-bit data items. cpu_proclk this is a reference signal for external bus cycles, which oscillates at the processor clock frequency. cpu_rw this signal indicates whether the current cycle is a read or a write cycle. during writes, the signal is asserted low at the beginning of the access (i.e. at the start of rastime for dram banks and at the start of cstime for sram / peripheral banks) and de-asserted high at the end of the access (end of castime / cstime). at all other times this signal is held high. cpu_wait wait states can be generated by taking cpu_wait high. cpu_wait is only sampled during sram or periph- eral accesses. cpu_wait retains the state of any strobe during the cycle after the one in which it was asserted, until it is de- asserted. when cpu_wait is de-asserted the access continues as programmed by the configuration inter- face. the cpu_wait signal can be treated as synchronous or asynchronous to the cpu_proclk clock, depending on the state of a bit 5 in the emi_configpadlogic register. this pin can not be disabled by software. if it is not used, this pin should be pulled down with a resistor. table 36 programmable cpu interface pin descriptions
c o n f i d e n t i a l STI5518 8 programmable cpu memory interface 7170179 d 65/294 notcpu_be[0:1] the emi uses word addressing, two byte-enable strobes are provided, and the use of the byte enable pins depends on the bus width. 16-bit wide memory is defined as an array of 2-byte words: 31 address-bits in the st20 memory space select a 2-byte word and ? notcpu_be[0:1] ? selects one byte within the word. 8-bit wide memory is defined as an array of 1-byte words with 32 address-bits selecting a word. for 8-bit wide memory, the lower order address bit (a0) is multiplexed onto the unused byte-enable pin notcpu_be[1] to give a 32-bit address bus. this address bit can be made available to the address bus by configuring the bank width as below. for banks configured as sdram, notcpu_be pins provide dq mask signals. for banks configured as dram, notcpu_be strobes are valid from the start of castime to one phase before the end of castime. for banks configured as sram, notcpu_be pins used as data-enable strobes have the same timing and may be configured to be active on read cycles, write cycles, or both read and write cycles. notcpu_cas[0:1] the two notcpu_cas[0:1] strobes have different meanings depending on the contents of banks 0 & 1 - dram (bank and byte mode), sdram and sram. the three configurations are described below. pin function table 36 programmable cpu interface pin descriptions pin 16-bit external port size 8-bit external port size notcpu_be[1] enables cpu_data[8:15] notcpu_addr[0] notcpu_be[0] enables cpu_data[0:7] enables cpu_data[8:15]
c o n f i d e n t i a l 8 programmable cpu memory interface STI5518 66/294 7170179 d notcpu_cas[0:1] dram configuration the cas strobes can be programmed on a per-bank basis in one of two modes. bank mode in which only one cas strobe is used for the entire bank and sub-banks (if any). byte mode in which each cas strobe is used as a byte decoded cas strobe and can be used across both banks (and any sub-banks). byte mode supports 16-bit wide drams or dram modules that provide multiple cas strobes, one for each byte, and a single write signal for byte write operations. the alternative type drams that have multiple write signals, one for each byte, and a single cas to allow byte write operations or banks that are constructed from 1, 4, or 8-bit wide drams can be interfaced using bank mode. note bank or byte mode can be selected independently for banks 0 and 1. cas strobes in bank mode (dram) if banks 0 and1 are set to dram device type with bank mode selected then notcpu_cas[0] is the sole cas strobe for bank 0 and notcpu_cas[1] is the sole cas strobe for bank1. unused cas strobes remain inactive during an access. cas strobes in byte mode (dram) for banks containing dram, which require byte decoded cas strobes, one programmable cas strobe is allo- cated to each byte. each of the cas strobes in this mode will have the timing programmed into the cas timing configuration registers, of the bank being accessed, if they are active during that cycle. byte mode cas strobes are active during an access if the byte corresponding to the strobe is being accessed. during refresh cycles, all cas strobes will go low at the start of the cycle and remain low until the end of the cycle. the table below shows how the cas strobes are used in byte mode. note that the strobes are common to both banks and any sub-banks. only the cas strobes that enable bytes which are being accessed will be active dur- ing an access cycle. the table below summarizes the byte mode notcpu_cas[0:1] strobe pins mixing bank and byte mode (dram) for full flexibility, any permutation of bankwidth cas mode (byte / bank) is supported for both banks 0 and 1. the following table gives a full listing of the active strobes for all permutations pin function table 36 programmable cpu interface pin descriptions cas strobe bank 0, 16-bits wide bank 1, 16-bits wide notcpu_cas[1] enables cpu_data[8:15] enables cpu_data[8:15] notcpu_cas[0] enables cpu_data[0:7] enables cpu_data[0:7] no of drams bank configuration notcpu_cas[0] notcpu_cas[1] one dram in bank0 or 1 bank mode active unused byte mode active cpu_data[0:7] active cpu_data[8:15] two drams in bank 0 and1 dram in bank0 bank mode active unused dram in bank0 byte mode active cpu_data[0:7] active cpu_data[8:15] dram in bank1 bank mode unused unused dram in bank1byte mode active cpu_data[0:7] active cpu_data[8:15]
c o n f i d e n t i a l STI5518 8 programmable cpu memory interface 7170179 d 67/294 notcpu_cas[0:1] sdram configuration notcpu_cas[0:1] sram configuration for banks which do not contain sdram or dram the notcpu_cas[1] pin is inactive. if there is no sdram or dram at all on the programmable cpu interface, notcpu_cas[0] is cpu_addr[22] to allow up to 8mbytes sram addressing. notcpu_ce[0:3] these four signals are used for programmable strobe (for example, chip select when the corresponding bank is configured as sram/peripheral when sram/dram is used on the corresponding cpu interface, notcpu_ce[0:3] is used as the ras signal. notcpu_oe the behavior of the notcpu_oe signal depends on the type of memory being accessed. if the access is to a bank configured as dram then the notcpu_oe strobe is active only during a read access when it is asserted low case1time after the start of castime, and de-asserted high at the end of castime. for accesses to configured as sram / peripheral the notcpu_oe strobe is programmable and will behave according to the values in the emiconfigdata registers for that bank. notcpu_ras[0:1] these two signals control the ras strobe for sdram and dram. the two signals do not necessarily corre- spond to individual banks. bank0 (only) may be sub-decoded. for dram, notcpu_ras[0:1] strobes are used as the ras strobes for bank0, bank1, or sub-banks. for sdram, one ras strobe is used for all devices in the bank, and sub-decoding is carried out using the notcpu_ras[1] and notcpu_cas[1]pins. if bank0 is not programmed as sdram or dram, the notcpu_ras[0] strobe is used as chip-select (notcpu_ce[0]) for the bank. the table below summarizes the notcpu_ras[0:1] strobes for banks 0 and 1. pin function table 36 programmable cpu interface pin descriptions no of drams notcpu_cas[0] notcpu_cas[1] one sdram in bank0 or one sdram in bank1 active (cas strobe for sdram) active chip select for sdram one sdram in bank0 or one sdram in bank1 active (cas strobe for both sdrams) active chip select for sdram in bank 0 signal type definition notcpu_ras[0] out ras strobe for sdram/dram in bank 0, or ras strobe for lowest dram sub-bank in bank0, or chip select for bank0 notcpu_ras[1] out ras strobe for sdram/dram in bank1, or ras strobe for highest dram sub-bank in bank0, or sdram chip select signal for highest sub-bank of bank0 bank configuration notcpu_ras[0] notcpu_ras[1] bank 0: dram with no sub-decoding bank 0 ras strobe unused for bank0 bank 0: dram with two sub-banks bank 0 sub-bank0 ras strobe bank 0 sub-bank1 ras strobe bank 0: sdram with no sub-decoding bank 0 ras strobe unused for bank0 bank 0: sdram with two sub-banks bank 0 sub-bank0 ras strobe bank 0 sub-bank1 with chip select bank 0: sram / peripherals bank 0 chip select strobe bank3 sub-decoding bank 1dram with no sub-decoding bank 1ras strobe unused for bank1 bank 1dram with two sub-banks not possible not possible bank 1: sdram with no sub-decoding bank 1 ras strobe unused for bank1 bank 1: sdram with two sub-banks not possible not possible bank 1contains sram / peripheral unused for bank1 bank3 sub-decoding
c o n f i d e n t i a l 8 programmable cpu memory interface STI5518 68/294 7170179 d 8.2 configuration list the following tables illustrate the different configurations supported by sdram, dram and peripheral memories, the different strobes used in each case. note that it is not possible to have sdram and dram on the emi at the same time. emi bank configuration strobes bank0 bank1 bank2 bank3 peripheral peripheral peripheral peripheral notcpu_ce[0] for bank0, notcpu_ce[1]for bank1, notcpu_ce[2]for bank2 and notcpu_ce[3]for bank3. notcpu_ras1 available to subdecode bank3 notcpu_cas0 is cpu_add[22] to allow up to 8 mbytes of sram addressing notcpu_cas1 not used notcpu_oe shared by each bank notcpu_be[1:0] shared by each bank cpu_r/w shared by each bank cpu_wait shared by each bank dram peripheral peripheral peripheral if dram in bank 0: notcpu_ce[1] for bank1 if dram in bank1: notcpu_ce[1] for bank0 notcpu_ce[2]for bank2 notcpu_ce[3]for bank3 notcpu_ce[0] (ras0) for dram despite of dram position notcpu_cas0 (cas0) used by dram notcpu_cas1 (cas1) used by dram only if multi-byte mode enabled if dram in (and only in) bank0, then subdecoding up to 2 dram sub-banks using cpu_ras1 if dram in bank0 and no dram subdecoding or dram in bank1, cpu_ras1 available to subdecode bank3 notcpu_oe shared by each bank notcpu_be[1:0] shared by each bank. cpu_r/w shared by each bank. cpu_wait shared by each bank or peripheral dram peripheral peripheral table 37 list of strobes used for all emi configurations
c o n f i d e n t i a l STI5518 8 programmable cpu memory interface 7170179 d 69/294 dram dram peripheral peripheral notcpu_ce[0] (ras0) for dram in bank0, notcpu_ras1 for dram in bank1, notcpu_ce[2] for bank2, notcpu_ce[3] for bank 3, notcpu_ce[1] not used. no subdecoding is allowed for either dram. no subdecoding of bank3 multi-byte mode can be allowed for both drams at the same time: if multi-byte mode is not enabled: notcpu_cas0 for dram in bank0 notcpu_cas1 for dram in bank1 if multi-byte mode is enabled: notcpu_cas0 used as shared by both drams notcpu_cas1 used as shared by both drams notcpu_oe is shared by each bank notcpu_be[1:0] is shared by each bank. cpu_r/w shared by each bank. cpu_wait shared by each bank sdram peripheral peripheral peripheral if sdram in bank 0: notcpu_ce[1] for bank1, if sdram in bank1: notcpu_ce[1] for bank0 in both above cases (only 1 sdram): notcpu_cas1 used as chip select (sdram_cs(0)) for sdram notcpu_ce[0] used as ras0 strobe for sdram notcpu_cas0 used as cas0 strobe for sdram notcpu_ras1 used to subdecode bank3 if two sdram in bank0 (sdram subdecoding in bank0): notcpu_cas1 used to map sdram_cs(0) for sdram 0 notcpu_ras1 used to map sdram_cs(1) for sdram 1 (note: in this case not possible subdecode bank3) notcpu_ce[0] used as shared ras0 strobe by both sdrams notcpu_cas0 used as shared cas0 strobe by both sdrams in any case: notcpu_ce[2] for bank2 and notcpu_ce[3] for bank3 notcpu_oe shared by each bank notcpu_be[1:0] (with dqm functionality for sdram) shared by all banks cpu_r/w shared by each bank. cpu_wait shared by each bank or peripheral sdram peripheral peripheral emi bank configuration strobes bank0 bank1 bank2 bank3 table 37 list of strobes used for all emi configurations
c o n f i d e n t i a l 8 programmable cpu memory interface STI5518 70/294 7170179 d 8.3 external bus cycles the external memory interface supports dynamic memory and other devices such as static memory and io devices. this flexibility is provided by allowing the required wave-forms to be programmed via configuration registers (see section 8.4: emi configuration on page 80). memory is byte addressed, with words aligned on four-byte boundaries and half-words on two-byte boundaries. during read cycles, byte-level addressing is performed internally by the STI5518. the emi can read bytes, half-words or words. it always reads the size of the bank. during write cycles, the STI5518 uses the notcpu_be[0:1] strobes to perform addressing of bytes. if a particular byte is not to be written then the corresponding data outputs are tri-stated. writes can be less than the size of the bank. the internally generated address is indicated on pins notcpuaddr[1:21, 22]. the least significant bit of the data bus is always cpu_data[0]. the most significant bit is adjusted dynamically to suit the required external bus size. the following sections describe the access cycles for the three device types, dram, sdram and sram/peripherals. sdram sdram peripheral peripheral notcpu_cas1 used as chip select (sdram_cs(0)) for sdram in bank0 notcpu_ras1 used as chip select (sdram_cs(2)) for sdram in bank1 notcpu_ce[2] for periph in bank2 notcpu_ce[3] for periph in bank3 notcpu_ce[0] used as shared ras strobe for both sdrams notcpu_ce[1] not used notcpu_cas0 used as shared cas strobe by both sdram no subdecoding is allowed for both sdrams. no subdecoding of bank3. notcpu_oe shared by each bank notcpu_be[1:0] (with dqm functionality for sdram) shared by each bank. cpu_r/w shared by each bank. cpu_wait shared by each bank emi bank configuration strobes bank0 bank1 bank2 bank3 table 37 list of strobes used for all emi configurations
c o n f i d e n t i a l STI5518 8 programmable cpu memory interface 7170179 d 71/294 8.3.1 dram dram access cycles are supported in banks 0 and 1 only when these are set to device type dram. the emi can support either one dram bank set in one of the 4 possible banks or two dram banks set in bank0 and bank1. a dram memory access cycle consists of a number of defined periods or times, as shown in the figure below. all of the named times shown in this diagram together with other parameters such as ras address shift and page size are programmable to suit a wide variety of dram types. figure 18 dram memory cycle notcpu_be[0-1] constant high for reads constant high for reads read data latch time cpu_addr start of cycle rastime castime prechargetime row column rase1time rase2time case1time case2time case1time bus release time data in data bus (read) 1 phase data out data drive delay cpu_data (write) cpu_rw notcpu_oe (read) not_cas[0-1] not_ras[0-1]
c o n f i d e n t i a l 8 programmable cpu memory interface STI5518 72/294 7170179 d signals rastime and castime are consecutive. the castime can be followed by concurrent precharge and busrelease times. thus for dram, these times are used for ras address latching, cas address latching, ras precharge and output driver tristate times respectively. for consecutive access to the same bank of dram, rastime will only occur when there is a page miss. the next access will not commence until the prechargetime for a previous access to the same bank has completed. during the rastime, a transition can only be programmed on the ras strobes. during the castime the cas strobes and either the byte-enable or notcpu_oe strobes are active. the address is output on the address bus without being ras shifted. write data is valid during castime. read data is latched into the interface at the point defined by the latchpoint bit in the emiconfigdata3 register for the bank being accessed. the prechargetime and busreleasetime commence concurrently at the end of the castime. a prechargetime will occur, and the active notcpu_ras strobe will be taken high if: the next access is to the same bank but to a different row address; the next access is to a different bank. the busreleasetime runs concurrently with the prechargetime and will occur if: the current cycle is a read and the next cycle is a write; the current cycle is a read and the next cycle is a read from a different bank. the busreleasetime is provided to allow an accessed device to float to a high impedance state. page mode dram pages are delineated using the rasbits configuration parameter. these bits are used as an address mask for comparison with the previous dram address. if an access is requested by an internal subsystem of the STI5518 to a dram bank while a dram access is in progress, the new address is compared to the current access address. if the row addresses are the same, the access may proceed as a page mode access. there is no specific configuration bit to select pagemode dram. if all the r asbits are set to 0, t hen no pagehits will be caused and normal dram ras/cas cycles will always be produced.
c o n f i d e n t i a l STI5518 8 programmable cpu memory interface 7170179 d 73/294 a page mode access does not include the rastime period. the notcpu_ras strobe is not taken high before commencing the page mode access. if the current access is a read and the page mode access is due to be a write, a busreleasetime is inserted as shown in figure below. the notcpu_ras strobe is held low during this period. when setting the rasbits, care must be taken to consider the port size. also, if the bank has been sub-decoded, the sub-bank selection address bits must be included in the comparison, so the rasbits corresponding to these addresses must be set. for example, if the dram bank is composed of 2 x 256k * 16 devices, the sub-bank selection address bit is a19, so the rasbits corresponding to address bits a 19 -a 10 must be set. when page mode is active, the rase2time must be programmed to zero. figure 19 read followed by page mode write subbank subbanksize portsize subbank selection address ras strobe selection 2 256k 1m 4m 16m 8 bit address<18> address<20> address<22> address<24> 0 = notcpu_ras[0] 1 = notcpu_ras[1] 256k 1m 4m 16m 16 bit address<19> address<21> address<23> address<25> 256k 1m 4m 16m 32 bit address<20> address<22> address<24> address<26> table 38 address decoding notcpu_ras notcpu_cas notcpu_oe cpu_data castime rastime ras e1 time cas e1 time ras e2 time cas e2 time busrelease time prechargetime read data latch point cas cas castime read data write data row column m column n e1 time e2 time notcpu_be
c o n f i d e n t i a l 8 programmable cpu memory interface STI5518 74/294 7170179 d refresh dram banks are periodically refreshed at intervals specified by the refresh interval configuration parameter. the notcpu_cas strobe(s) is taken low at the beginning of the refresh time. the position of the ras falling edge (rasedge) is programmable and the minimum width of the cas pulse is the sum of the rastime and castime values specified for random access. if there is more than one bank of dram the refresh configuration will then be taken from the lowest numbered bank configured as dram. all sub banks are refreshed in the same access and a cycle is inserted between each bank and/or sub-bank in order to spread current peaks. if no dram has been programmed for a bank then no transitions occur on the relevant ras or cas strobes and all unused ras and cas strobes (i.e. strobes not used due to the choice of bank/byte mode, sub- banks and bankwidth) will remain inactive during a refresh cycle. the emi ensures that notcpu_cas and notcpu_ras are both high for the required time before every refresh cycle by inserting a prechargetime in the last bank being accessed and ensuring all prechargetimes are complete. note, no refreshes will take place until after a draminitialize command in the configcommand register is performed. figure 20 generic refresh access for one dram bank figure 21 generic refresh access for two dram banks name programmable value prechargetime 1 - 8 cycles refreshinterval (1 - 16) * 128 cycles refreshrasedgetime 1 or 2 cycles after start of refresh table 39 refresh parameters notcpu_cas notcpu_ras[0] notcpu_ras[1] rastime + castime refreshrasedgetime 1 cycle start of refresh end of refresh 2 sub banks 2 sub banks only prechargetime no sub banks notcpu_cas3-0 notcpu_ras[0] notcpu_ras[1] rastime + castime refreshrasedgetime 1 cycle start of refresh end of refresh 2 sub banks 2 sub banks only prechargetime no sub banks
c o n f i d e n t i a l STI5518 8 programmable cpu memory interface 7170179 d 75/294 8.3.2 sdram note these diagrams show the waveforms at device?s pads, not the outputs from the generic emi block. typically the emi pad logic will re-time the emi ? s outputs to the next cycle. all signals on this interface are synchronous to the system clock, which is fed to the sdrams on the cpu_proclk pad. 8.3.2.1 typical access the following diagrams shows typical read and write accesses to an sdram. this example shows a bank activation, due to a page miss, then two write accesses in the same bank are performed in page mode. a precharge is then done in anticipation of another bank activation command. if as in this example only one sdram word is to be written then the notcpu_be signal is used as a data mask, so that only the correct word is updated. figure 22 sdram write accesses notcpu_ras notcpu_cas cpu_rw cpu_data activatetowrite (write) prechargetime data drive delay cpu_addr row col (dqm) (not_we) (not_cas) (not_ras) bank write activate cpu_proclk notsdramcs (not_cs) col writerecoverytime precharge all ap=1 nop nop nop notcpu_be[
c o n f i d e n t i a l 8 programmable cpu memory interface STI5518 76/294 7170179 d the following figure shows a bank activation, due to a page miss, then two read accesses in the same bank are per- formed in page mode. a precharge is then done in anticipation of another bank activation command. if as in this exam- ple only one sdram word is to be read then the notcpu_be signal is used as a data output enable. figure 23 sdram read accesses with cas latency = 2 cycles notcpu_ras notcpu_cas cpu_rw notcpu_be cpu_data activatetoread (write) prechargetime cpu_addr row col (dqm) (not_we) (not_cas) (not_ras) bank read activate cpu_proclk notsdramcs (not_cs) n col m cas latency =2 precharge all ap=1 nop nop busreleasetime dqm high to data out forced to high-z equals to 2 clock cycles (fixed dqm latency for reads)
c o n f i d e n t i a l STI5518 8 programmable cpu memory interface 7170179 d 77/294 figure 24 sdram read accesses with cas latency = 3 cycles notcpu_ras notcpu_cas cpu_rw notcpu_be cpu_data activatetoread (write) prechargetime cpu_addr row col (dqm) (not_we) (not_cas) (not_ras) bank read activate cpu_proclk notsdramcs (not_cs) n col m cas latency = 3 precharge all ap=1 nop nop busreleasetime nop dqm high to data out forced to high-z equals to 2 clock cycles (fixed dqm latency for reads)
c o n f i d e n t i a l 8 programmable cpu memory interface STI5518 78/294 7170179 d 8.3.3 sram or peripheral access cycles a generic peripheral (e.g. sram, eprom, flash, etc.) type of access is provided which is suitable for direct interfacing to a wide variety of sram, rom, flash and other peripheral devices. no internal sub-decoding is provided with banks in this configuration. all of the named times shown in section 8.3.4 together with other parameters such as bank size and bank size dependent shifts are programmable to suit a wide variety of device types. for details of the configuration of the emi see section 8.4: emi configuration on page 80. the distance between signal time pairs oee1/oee2 and bee1/bee2 is primarily set by the registers emi_configdata1bank and emi_configdata2bank. if this distance is set to maximum by these registers, then an additional delay of up to 3 wait cycles can be inserted for peripheral accesses to the upper portion of emibank3, using the emi_configpadlogic register bit waitcycles. these bits control a wait period that is inserted both at the start of the emi access cycle and at the end (triggered by the cs low-to-high transition). for a 60 mhz clock, this gives a maximum additional delay of 133ns. figure 25 generic peripheral access read data latch point busrelease time data drive delay cse1 time cse2 time oee1 time bee1 time be e2 time accesscycletime cpu_addr notcpu_oe notcpu_be cpu_data (write) cpu_data (read) oee2time cpu_rw write constant high for reads constant high for reads notcpu_ce
c o n f i d e n t i a l STI5518 8 programmable cpu memory interface 7170179 d 79/294 8.3.4 wait cpu_wait is provided so that external cycles can be extended to enable variable access times, for example, shared memory access. cpu_wait is only effective during accesses to sram / peripheral banks and is ignored during accesses to dram banks. the STI5518 can accept either synchronous or asynchronous cpu_wait signals. if cpu_wait is synchronous, then wait states can be inserted at precise times during the access. an asynchronous cpu_wait does not require any external synchronization but cannot accurately insert wait states during an access. the following description and diagrams assume that a synchronous cpu_wait is being used. the cpu_wait signal can be enabled on a per-bank basis. note that the selection of the asynchronous or synchronous cpu_wait signal is the same for all banks. cpu_wait freezes the state of the strobes for the duration of the cycles in which it was sampled high. any strobe transitions occurring on the sampling edge or the falling edge immediately after this will not be inhibited, however, transitions on the rising and falling edges of the following cycle w ill not occur. the following two figures illustrate the extension of the external memory cycle and the delaying of strobe transitions. the asynchronous cpu_wait uses an extra clock edge to synchronize the signal before it is sampled in the emi. apart from this extra cycle of latency, the response to the two types of cpu_wait is the same. configuration of the cpu_wait pin to a synchronous or asynchronous wait signal is performed by bit 5 of the emi_configpadlogic register. setting this bit high selects a synchronous wait signal, setting it low selects an asynchronous wait signal. note the asynchronous cpu_wait does not need to meet setup and hold times to the cpu_proclk signal rising edges. figure 26 strobe activity without cpu_wait figure 27 strobe activity with cpu_wait cpu_proclk cpu_wait strobe1 strobe2 strobe3 cpu_proclk cpu_wait asserted wait cycle cpu_wait strobe1 strobe2 strobe3
c o n f i d e n t i a l 8 programmable cpu memory interface STI5518 80/294 7170179 d 8.3.5 bank-width based address shifting address shifting can be enabled on a per bank basis to allow population options on boards which vary bank widths to be handled more easily. the shifts can only be enabled in banks programmed to the sram or peripheral device type, the shift amount being dependent on the width of the bank. shifting is enabled or disabled by 4 bits, one for each bank, of the emi padlogic register configpadlogic0-3 where bit 0 refers to bank 0 and so on. the table below shows the addresses presented on the cpu_addr[1:21] pins for different configurations. note that the addresses presented on the notcpu_be[0:1] signals for 16 or 8 bit banks are not affected by the shifting. 8.4 emi configuration the emi configuration is held in memory-mapped registers. the function of the registers is to eliminate external decode and timing logic. each emi bank has several parameters which can be configured. the parameters define the structure of the external address space and how it is allocated to the four banks and the timing of the strobe edges for the four banks. each emi bank has 64 bits of configuration data which is held in four 16-bit configuration registers in addition there is an emiconfiglock register for each bank, an emiconfigstatus register, the emidraminitialize register and an emiconfigpadlogic register. for safe configuration, each of the four banks should be configured after reset and then have their configuration locked by writing to the emiconfiglock register before any access to an external bank is made. 8.5 default configuration the default configuration is loaded into all four banks on reset. it should allow the emi to read data from a slow rom memory. the following parameters are set. bank device type configpadlogic0-3 current_portsize<1:0> cpu_addr[1:21] dram - -- address2-23 during cas time sram or peripheral 0 = shift disabled 1 = shift enabled 01 (32 bit) address2-23 10 (16 bit) address1-22 11 (8 bit) address0-21 table 40 sram address shifting parameter default value datadrivedelay 101 (5 phases) busreleasetime 10 (2 cycles) csactive 01 (active during read only) oeactive 01 (active during read only) beactive 00 (inactive) portsize value of the signal portsize_init devicetype 000 (peripheral) accesstimeread 1000 (8+2=10 cycles) cse1timeread 00 (0 phases) cse2timeread 00 (0 phases) oee1timeread 00 (0 phases) oee2timeread 00 (0 phases) latchpoint 00 (end of access cycle) table 41 default configuration
c o n f i d e n t i a l STI5518 8 programmable cpu memory interface 7170179 d 81/294 figure 28 default configuration for sdrammodereg0/1 registers sdrammodereg0/1 latency mode burst type burst length 15:7 6:4 3 2:0 000000000 010 0 010 table 42 default configuration for sdrammodereg0/1 registers cpu_data (write) cpu_addr notmemcs notcpu_oe cpu_data (read) 10 cycles 5 phases 2 cycles read data latch point
c o n f i d e n t i a l 9 system services STI5518 82/294 7170179 d 9 system services the system services module includes all of the necessary logic to initialize the device. device initialization and debugging can also be done with the diagnostic controller unit (dcu); see the diagnostic controller on page 83 . 9.1 power-on hard reset the reset pin provides a power-on or ? hard ? reset function. it must be asserted (low) before the clocks and power supply are stable. when the r eset pin is asserted (regardless of any other inputs), all modules are asynchr onously forced into their power-on reset state. the reset pin should only be de-asserted (high) after both of the following events have taken place: the clocks and power are stable, to guarantee well-defined behavior; the nottrst tap reset pin has been asserted. when the reset pin is de-asserted, the cpu enters its boot sequence. the sequence starts only after the rising edge of the reset pin is internally synchronized and the clocks are stable. bootstrap code can either be in off-chip rom or can be received through the dcu. 9.2 bootstrap the STI5518 can be bootstrapped from the diagnostic controller (dcu), or from rom. booting from the dcu the STI5518 can be booted from the dcu at any time by setting up the test access port (tap) to do so. the procedure is explained in the diagnostic controller chapter. if the device is not set up to boot from dcu then the STI5518 w ill boot from rom as soon as it comes out of reset. booting from rom when not booting from dcu, the boot_from_rom pin sets the STI5518 to boot from rom as it comes out of reset. if the boot_from_rom pin is high, boot code is run from a slow external rom placed in bank 3 at the top of memory. the rom width is 16-bit wide. when booting from rom, the value in the configuration registers for the portsize for bank 3 is disregarded. when booting from rom, the STI5518 starts to execute code from the top two bytes in external memory, at address #7ffffffe, which should contain a backward jump to a bootstrap program in rom.
c o n f i d e n t i a l STI5518 10 diagnostic controller 7170179 d 83/294 10 diagnostic controller the st20 diagnostic controller unit (dcu) is used to boot the cpu and to control and monitor all of the systems on the chip, via the standard i eee 1194.1 test access port. the dcu includes on-chip hardware with ice (in circuit emulation) and lsa (logic state analyzer) features to facilitate verification and debugging of software running on the on-chip cpu in real time. it is an independent hardware module with a private link from the host to support real-time diagnostics. 10.1 diagnostic hardware the on-chip diagnostic controller assists in debugging, while reducing or eliminating the intrusion into the target code space, the cpu utilization, and impact on the application. as shown in figure 29 , the dcu and tap provide a means of connecting a diagnostic host to a target board with a suitable jtag port connector and interface. the diagnostic controller provides the following facilities for debugging from a host: control of target cpu and subsystems including cpu boot; hardware breakpoint, watchpoint, datawatch and single instruction step; complex trigger sequencing and choice of subsequent actions; non-intrusive jump trace and instruction pointer profiling; access to the memory of the target while the device is powered up, regardless of the state of the cpu; full debugging of rom code. when running multi-tasking code on the target, one or more processes can be single-stepped or stopped while others continue running in real time. in this case, the running threads can be interrupted by incoming hardware interrupts, with a low latency. the host can communicate with the dcu via a private link, using the 5 standard test pins. target software also has access to the diagnostic facilities and access through the dcu to the host memory. a logic state analyzer can be connected to the trigger_in and trigger_out pins. the response to trigger_in and the events that cause a trigger_out signal can be controlled by the host or by target software. the diagnostic controller provides debugging facilities with much less impact on the software and target performance. in particular it gives: non-intrusive attachment to the host system; no intrusion into the performance of the cpu or any subsystems; figure 29 debugging hardware host host interface te s t access port diagnostic controller st20 logic state analyzer
c o n f i d e n t i a l 10 diagnostic controller STI5518 84/294 7170179 d no intrusion into the code space, so the application builder does not need to add a debugging kernel; no intrusion into any on-chip functional modules, including any communications facilities; no functional external connection pins are used. the connections between the diagnostic controller and other on-chip modules and external hardware may vary between st20 variants. 10.2 access features access to target memory and peripheral registers from host full read and write access to the entire on-chip and external memory space and the register space is available via the tap. this is independent of the state of the cpu. access from target cpu process the cpu itself can program its own diagnostic controller. further access may be explicitly prevented by the lock mechanism so that the application being debugged cannot interfere with the breakpoint and watchpoint settings. when the breakpoint or watchpoint match occurs, then the diagnostic controller may release the lock according to settings in the control register. access to host memory from target if the target cpu accesses any address in the top half of the dcu memory space, then these accesses are mapped on to host memory via the tap as target initiated peek and poke messages. peek accesses and poke accesses are specifically enabled by separate property bits. 10.3 software debugging features control of the target cpu including boot various state information about the target cpu may be monitored and the cpu may be controlled from the diagnostic controller via the tap. the control of the cpu extends to stalling, forcing a trap and booting. non-intrusive iptr profiling a copy of the iptr is visible as a read-only register in the diagnostic controller. this register may be read at any time. reading this register is not intrusive on the cpu or its memory space. events support is provided by the diagnostic controller to trigger actions when certain predefined events occur. event action breakpoint the function of the breakpoint is to break before the instruction is executed, but only if it really was going to be executed. a 32-bit comparator is used to compare the breakpoint register against the instruction pointer of the next instruction to be executed. the matched instruction is not executed and the cpu state, including all cpu registers, is defined as at the start of the instruction. the previous instruction is run to completion. breakpoint range the function of a breakpoint range is equivalent to any single breakpoint but where the breakpoint address can be anywhere within a range of addresses bounded by lower and upper register values. table 43 software debugging events
c o n f i d e n t i a l STI5518 10 diagnostic controller 7170179 d 85/294 following a watchpoint match, or any other condition detectable by the diagnostic controller, the subsequent action may be programmed to be one of the following: stall the cpu, i.e. inhibit further instructions from being executed by the cpu; wait until the end of the current instruction, then signal a hardware trap; signal an immediate hardware trap; continue without intrusion. in addition, the diagnostic controller may take any combination of the following actions: signal on trigger_out to a logic state analyzer; send a triggered message via the tap to the host; unlock access by the target cpu. hardware single instruction step the function of single stepping one cpu instruction is performed by using a breakpoint range over the code to be single stepped. the dcu includes a mechanism to prevent the breakpoint trap handler single-stepping itself. by selecting an inverse range, the effect of single stepping one high level instruction can be achieved. jump trace jump tracing monitors code jumps, where a jump is any change in execution flow from the stream of consecutive instructions stored in memory. a jump may be caused by a program instruction, an interrupt or a trap. when the jump occurs, a 32-bit dcu register is loaded with the origin of the jump. this value points to the instruction which would have been executed next if the jump had not occurred. the cpu may not have completed the instruction prior to the change in flow. the diagnostic controller can be set to trace the origin of each jump, the destination, or both. the dcu copies the details of each jump to a rolling trace buffer in memory. the trace buffer may be located in host memory, but using target memory will have less impact on performance. the tracing facility has two modes: low intrusion. in this mode the dcu uses dead memory cycles to write the trace into the buffer. this means that the cpu is not delayed, but some trace information may be lost. complete trace. in this mode, the cpu is stalled on every jump to ensure the data can be written to the buffer. this means that no trace information is lost, but the cpu performance is affected. logic state analyzer (lsa) support two signals, trigger_in and trigger_out, are provided to support diagnostics with an external lsa. the action by the dcu on receiving a trigger_in signal is programmable. the selection of internal events which trigger a trigger_out signal is also programmable. watchpoint the function of a watchpoint is to trigger after a memory access is made to an address within the range speci- fied by a pair of 32-bit registers. the cpu pipeline architecture allows for the cpu to continue execution of instructions without necessarily waiting for a write access to complete. so, by the time a watchpoint violation has been detected, the cpu may have executed a number of instructions after the instruction which caused the violation. if the subsequent action is to stall the cpu or to take a hardware trap, then the last instruction exe- cuted before the stall or trap may not be the instruction which caused the violation. datawatch the function of a datawatch is to trigger after a data value specified in one 32-bit register is written to a memory word address specified in another 32-bit register. the subsequent action is equivalent to a watchpoint. event action table 43 software debugging events
c o n f i d e n t i a l 10 diagnostic controller STI5518 86/294 7170179 d trigger combinations and sequences complex trigger conditions can be programmed. for example: the fifth time that breakpoint 3 is encountered; enable a watchpoint when a breakpoint occurs. there is no software intrusion imposed by this mechanism. 10.4 controlling the diagnostic controller this section gives a summary of host communications with the diagnostic controller. the diagnostic controller has direct access to: the instruction pointer, a selection of cpu state control signals, the memory bus, memory-mapped peripheral configuration registers. this access does not depend on the state of the cpu. access to non-memory-mapped peripheral configuration registers is via the cpu, and for this the cpu must be active and running the appropriate handler. the host can give two commands to the diagnostic controller: peek and poke . peek reads memory locations or configuration registers, and poke writes to memory locations or configuration registers. the diagnostic controller responds to a peek command with a peeked message, giving the contents of the peeked addresses. the diagnostic controller has registers, which are accessed from the host using peek and poke commands. the registers are used to control breakpoints, watchpoints, datawatch, tracing and other facilities. the target cpu can also access these registers using the normal load and store instructions, so the target software running on the cpu can program its own diagnostic controller. a lock is provided to prevent cpu access, which can be released by the diagnostic controller when a breakpoint or watchpoint match occurs. in addition, the target cpu can peek and poke the host via the diagnostic controller by reading or writing addresses in the top half of the memory space of the diagnostic controller. this facility can be disabled. various different types of cpu events can be selected as trigger events . when an trigger event occurs, the diagnostic controller can send a triggered message. the four types of message are summarized in the table below. the messages are distinguished by the two least significant bits of the message header byte. messages may be initiated from either the host or the target. target initiated messages, which constitute asynchronous or unsolicited messages, can be enabled by a property bit. message type direction bit 1 bit 0 meaning poke command. 0 0 write to one or more addresses. peek command. 0 1 read from one or more addresses. peeked opposite to peek command. 1 0 the result of a peek command. triggered dcu to host. 1 1 a trigger event has occurred. table 44 diagnostic controller message types
c o n f i d e n t i a l STI5518 10 diagnostic controller 7170179 d 87/294 messages are composed of a header byte followed by zero or more data bytes, depending on the type of message. the formats for the four message types are shown in figure 30 . 10.5 peeking and poking the host from the target the target cpu can peek and poke the host via the diagnostic controller. this is done by reading or writing a single word to a block of addresses within the dcu register block. the dcu will then send a peek or poke message to the host. after a host peek , the target cpu will wait until the host responds with a peeked message, which the dcu returns to the cpu as memory read data. peeking and poking the host from the target can be enabled or disabled. after reset, these bits are cleared, so peek and poke from the target are disabled. figure 30 message formats poke command messages response messages address first data word second data word peek address peeked first data word second data word third data word triggered header header header header
c o n f i d e n t i a l 11 test access port STI5518 88/294 7170179 d 11 test access port the STI5518 test access port (tap) conforms to ieee standard 1149.1. the tap has pins as listed in table 45 tdo can be over-driven to the power rails, and tck can be stopped in either logic state. none of the tap pins has an internal pull-up. the instruction register is 5 bits long with no parity. the pattern ? 00001 ? is loaded into the register during the capture- ir state. there are four defined public instructions, outlined inthe table below. all other instruction codes are reserved. there are three test data registers; bypass, boundary-scan and identification. these registers operate according to 1149.1. the operation of the boundary-scan register is defined in the bsdl description. identification code. cut identification the cut identification register (address 0x00000180) contains the product cut number coded as cut x.y, where decimal x occupies the 4 msbs as binary coded decimal (bcd) and decimal y occupies the 4 lsbs as bcd. pin in/out function tdi in test data input tdo out test data output tms in test mode select tck in test clock nottrst in test logic reset table 45 STI5518 tap pins instruction code 1 1. msb ... lsb; lsb closest to tdo. instruction selected register 0 0 0 0 0 extest boundary-scan 00010idcode identification 0 0 0 1 1 sample/preload boundary-scan 1 1 1 1 1 bypass bypass table 46 instruction codes bit 31 bit 0* mask rev b st20 family variant stmicroelectronics manufacturers id c 1d405041 00011101010000000101000001000001 table 47 identification code
c o n f i d e n t i a l STI5518 12 data flow 7170179 d 89/294 12 data flow this chapter describes the data flow through the STI5518, from the incoming transport stream to the outgoing analog video and pcm audio. it shows how the picture and sound modules are used together. the individual modules are described in the appropriate chapters. 12.1 on-chip modules the STI5518 reads in an mpeg2 transport stream, demultiplexes it, decodes the audio and video elementary streams and creates a video picture and audio pcm. demultiplexing extracts the video and audio mpeg streams plus other pes data such as dvb subtitles. hardware m odules are provided on-chip for decoding the mpeg video and audio. the data before decoding is called compressed data (cd), and digital video data after decoding is called pixel data. the on-chip modules which process the compressed data streams from the incoming transport stream to the decoders are shown below: figure 31 compressed data modules figure 32 decoded data modules dma cd unit: emi sub-picture decoder video decoder audio decoder video bit buffer audio bit buffer STI5518 64 32 st20 bus mpeg bus pes parser and cd fifos dvd/vcd/cd-da program front-end interface external sdram external sdram shared memory interfaces sub-picture decoder video decoder audio decoder display unit pcm audio analog video video frame store osd STI5518 mpeg bus mpeg and display memory interface pal/ntsc/ secam encoder (denc)
c o n f i d e n t i a l 12 data flow STI5518 90/294 7170179 d 12.2 video data flow the data flow for mpeg-2 video streams is illustrated below. dvd, vcd, and cdda data enters the STI5518 through the i 2 s, parallel, fec or atapi input. these data formats are described in front-end interface on page 92 . dvd data are descrambled by the css decryption module. dvd, vcd, and cdda data are transfered by dma (see link on page 105 ) to the track buffer which can be on the programmable cpu interface or the shared memory interface. the data in the track buffer is demultiplexed by software into seperate componatnts (video, audio, subpicture/ogt, navigation). video data enters the cd unit through the pes parser, which passes the data to the video cd fifo. the video cd fifo holds 128 bytes and writes 512-bit bursts into the video bit buffer in the sdram on the shared meory interface. the video decoder (described in mpeg video decoder on page 133 ) reads 1024-bit bursts from the video bit-buffer. it decodes the compressed bit stream and produces a pixel stream. i-frames and p-frames and b-frames are written into video frame stores. different programmable pointers allow enhanced trick modes. the display unit (described in display planes on page 156 ) converts the blocks of pixels into rows, and performs filtering (zoom-in, zoom_out...) and pan/scan. it then mixes the video with the other display planes and sends two pixel streams to the on-chip pal/ntsc/secam encoder (denc). one pixel stream is in 4:4:4 format and is generally used for tv display, while the other is in 4:2:2 format, and is generally used for output to a vcr. the denc converts the pixel streams into analog signals for output from the device. the 4:4:4 pixel stream is converted into yuv and rgb signals, and the 4:2:2 pixel stream is converted into cvbs and yc signals. figure 33 video data flow external sdram or dram pid filter (stb) css (dvd) link dma dvd fe fec input, i 2 s input, parallel input and atapi input. mpeg dma pes parser compressed data fifo pts/dts fifo external sdram video decoder external sdram display unit pal/ntsc/ secam denc dacs sector stream or pes stream pes stream elementary stream video bit-buffer smi smi 4:4:4 4:2:2 rgb or yuv y-c & cvbs emi or smi frame buffer
c o n f i d e n t i a l STI5518 12 data flow 7170179 d 91/294 12.3 audio data flow the data flow for audio streams is illustrated in the figure below. up to the track buffer, the audio data follows the same path as the video data flow described above. audio data are sent to the audio cd fifo and do not pass through the pes parser in the cd unit. the audio cd fifo writes 512-bit bursts into the audio bit buffer in external sdram on the shared memory interface. the cd unit is described in mpeg video decoder on page 133 . the audio decoder (described in audio decoder on page 219 ) unit includes its own fifo and pes parser. it transfers data from the audio bit-buffer into its fifo. the data may be either passed to the audio dsp or to an external audio interface for transfer to an external audio decoder (see external audio decoder interface on page 241 ). figure 34 audio data flow external sdram css link dma dvd fe i 2 s input, fec input, parallel input and atapi input. mpeg dma compressed data fifo external sdram serializer audio decoder sector stream or pes stream pes stream audio bit-buffer emi or smi fifo smi pes stream pes stream external audio interface dac_pcmout0 dac_pcmout1 dac_pcmout2 spdif_out
c o n f i d e n t i a l 13 front-end interface STI5518 92/294 7170179 d 13 front-end interface 13.1 introduction the figure below illustrates the front-end interface (fei) architecture. for stb applications, data enters through the fec interface. figure 35 link architecture parallel nrss interface st20 bus controller filter ram mux fei_gcf[0] mux mux mux fei_gcf[5] i 2 s serial interface fec interface dvd css decryption acquisition ram descrambler (reserved) transfer processor atapi sector processor dma sector processor transport processor link fei mux mux mux fei_gcf[12] fei_gcf[6] interface interface interface fei_atapi_cgf[1] fei_gcf[1] or fei_gcf[12] or fei_atapi_cgf[1]
c o n f i d e n t i a l STI5518 13 front-end interface 7170179 d 93/294 13.2 serial interface the dvd front-end serial interface supports many different formats and can be used for dvd, vcd and cd-da applications. for dvd applications, sectors of 2048, 2064, 2066... bytes are accepted. for vcd and cd-da applications, subcodes are multiplexed with data, and the cpu software demultiplexes the data. in serial mode, the STI5518 signals are renamed as in the table below. signal fec_data corresponds to the serial stream data and signal fec_b_clk corresponds to the serial stream clock. fec_b_clk can be up to 59.5mbits, or 60mbits if the clock is synchronized with the st20 clock. the fec_d_valid signal is active during a burst transmission (data are supposed to be transferred in a burst of at least 8 bits long). there can be gap of one or more clock cycles between bytes, but there can be no gaps within the 8 bits of a byte. when the fec_p_start signal is active during the first bit of the first byte of a packet, the serial front- end interface detects the beginning of a packet. the rising edge is detected on the fec_p_start pin and the internal fifo counter is reset. when accessing the link through the fei, the minimum delay between 2 consectutive sectors is ten serial interface clock cycles. s ignal name signal name in serial mode pin number type b_data fec_data 16 i b_bclk fec_b_clk 17 i b_flag fec_d_valid (dvd) fec_p_clock (dvb/dss) 18 i b_sync fec_p_start (dvd) fec_error (dvb/dss) 19 i table 48 serial mode signal names figure 36 dvd serial interface bit 1 bit 2 bit 3 bit n-1 bit n bit 1 bit 2 bit 3 bit n-1 bit n z z z z first bit of byte in sector fec_b_clk fec_data fec_d_valid fec_p_start micro is activating output burst transmission burst transmission
c o n f i d e n t i a l 13 front-end interface STI5518 94/294 7170179 d 13.3 dvb-ci mode (optional) this option is intended for set-top box applications using the digital video broadcast common interface (dvb-ci). all dvd modes are removed on versions with this option. the dvb-ci mode uses the three fec interface control pins (17, 18 and 19) , and the pio3 pins for the transport data: miclk is the data clock, as defined in the dvb-ci specifications (en 50221). the data mdi[7:0] are clocked out of the stv700/1 on the falling edge of miclk. the STI5518 samples this data on the rising edge of miclk in order to comply with the setup and hold times specified in the dvb-ci specifications. mistrt is valid only during the first byte of the input transport packet, that is, when mdi[7:0]=0x47. mival indicates valid data bytes on mdi[7:0]. mival may be either at logic 1 for the duration of the transport packet (burst valid data), or go to logic 0 at any time to indicate data bytes which must be ignored. to select the front-end mode, you have to program bit 0 of the fei configuration register, that is fei_gcf[0]. all the other bits of fei_gcf are related to dvd modes and have no effect on this mode: pin number pin name function pin type 6-13 pio3[0:7] mdi[0:7] input 17 b_bclk miclk input 18 b_flag mistrt input 19 b_sync mival input table 49 pin functions for the dvb-ci mode fei_gcf[0] = 0 dvb-ci compliant mode fei_gcf[0] = 1 fec mode.
c o n f i d e n t i a l STI5518 13 front-end interface 7170179 d 95/294 the diagram below shows how the different devices are connected together. you can insert either one dvb-ci module using stv701, or two dvb-ci modules using stv700. these ics are inserted between front-end and back-end products, such as the stv399 and the STI5518. 13.4 parallel interface the front-end parallel interface is a generic interface that can be used to input data directly to the decryption cell.this interface has the pins described in the table below: in order to ensure data continuity in the serializer (60mbit/s) at the input to the dma, there is an elastic buffer behind the asynchronous parallel interface. the handshake over the interface is controlled by the output signal para_req, which is, in effect, the "empty signal" for the 2-byte buffer. it goes active when the buffer requires more data. figure 38 , below, illustrates typical waveforms. the operation of the interface is as follows: figure 37 : satellite set-top box transport flow diagram using the dvb-ci pins name type function 13 - 6 (pio3[7:0]) para_data[7:0] i parallel input data bus 206 (pio2[2]) para_str i parallel input strobe 205 (pio2[1]) para_req o parallel output request 201 (pio1[5]) para_sync i parallel synchronization 196 (pio1[2]) para_dvalid i parallel input data valid table 50 parallel interface pins 8 module interface (pcmcia connector) smartcard stv720 STI5518 dvb-ci compliant stv700/701 tuner + adc + fec stv399 transport stream (serial or parallel) mistrt mival miclk mdi[7:0] smartcard reader lnb bypass mode dvb-ci module
c o n f i d e n t i a l 13 front-end interface STI5518 96/294 7170179 d when para_req is active then the data on the interface must be written to the buffer. para_req then goes inactive since the buffer is no longer empty. however, the buffer is not yet full since it is 2 bytes long; hence, a second byte can be written if desired. when the buffer needs more data para_req will again go active. in terms of fei clock cycles (of 60 mhz), para_req goes active after 8 cycles if 1 byte is written, and after 16 cycles if 2 bytes are written. when the last byte of a sector is written para_req will stay inactive for an additional 10 cycles (that is, 10+8 or 10+16 cycles). furthermore, following an encrypted sector, para_req stays inactive for an additional 10 cycles (that is, 10+8 or 10+16 cycles) after the first byte of the new sector is written. the dvd data entering the parallel interface are 2048-byte sectors (if the dvd header has been stripped by the front- end) or 2064-byte sectors (the sector length is defined in fei_slg register). the data latching signal is selected by register fei_gcf[13] as the rising edge (for non-inverted polarities) of either para_str, figure 38 , or (para_dvalid & para_str), figure 39 . the polarities of the signals para_str and para_req are programmable by register fei_gcf[3,4]. they must be set up before the parallel interface is selected (fei_gcf[1]). with inverted polarities, the clocking edge of para_str is the falling edge. the parallel interface is automatically configured when fei_gcf[1] is set. however, since all the parallel interface pins have alternate functions, they must be separately set to the correct i/o type. that is, each one must be set to ? input ? except para_req which must be set to ? output ? . the i/o type is set by registers pio_pnc2:0. the "sector start" signal can be either an external asynchronous input on pin para_sync or an internally generated signal using register fei_slg. the setup is via register fei_gcf[10,11]. figure 38 generic parallel interface waveforms (para_dvalid not used) figure 39 generic parallel interface waveforms (para_dvalid activated) para_str para_data[7:0] para_req tperiod / 2 tperiod tstr_to_req treq_to_str thold para_sync data 1 data 2 data 3 data 4 tsync_to_str data 2048 for timing values see table 129 on page 289 . tsetup optionally, a second byte can be written when para_req is inactive. para_str para_data[7:0] para_req para_sync data 1 data 2 data 3 data 4 data 2048 para_dvalid
c o n f i d e n t i a l STI5518 13 front-end interface 7170179 d 97/294 the para_sync signal may be used for example to process dvd shortened sectors (that is, sectors that have less than 2048 data bytes due to, for example, front-end disturbances which cause loss of sync). shortened sectors are completed to 2048 bytes by adding extra bytes after the next sync, that is, at the beginning of the following sector. this following sector is then ignored. the maximum width of para_sync is unlimited but it must be asserted 20ns before the first byte of the sector is written. the minimum width of para_sync is 20ns. the para_sync signal must not be active if para_req is inactive. 13.5 atapi interface introduction the ata interface (commonly known as atapi) is mainly used for mass storage peripherals in desktop computing. however, some consumer cost-effective dvd drives use the atapi interface. the STI5518 interfaces gluelessly to these drives. atapi drives are memory mapped devices. a set of registers and an interrupt, control the drive. data can be transferred in the following two ways: programmed input/output (pio), a memory mapped data register. this is also used to describe one form of data transfers; dma transfer. the atapi interface is accessed through bank 1 of the cpu programmable interface. connecting to the atapi drive the atapi drive uses the STI5518 programmable cpu interface for register io, and block move dma to move the data from the atapi to the decryption unit. only the pio modes up to mode 2 (read and write) are supported by the decryption unit. the databus width is 16-bits, and the data is connected to the STI5518 front-end interface internally. the st20 programmable cpu interface (otherwise called emi) must be programmed according to the dvd drive speed. the figure below shows how the atapi interface should be connected to the STI5518. operating the atapi interface the following signals are used to operate the atapi interface in pio mode: diow (device register write), write strobe signal atapi_wr dior (device register read), read strobe signal atapi_rd atapi enable (interface enable), notce[1] figure 40 connection of an atapi drive to the STI5518 fei dvd interface 8 data address atapi drive diow dior st20 16 STI5518 mux fei_atapi_cgf[1]
c o n f i d e n t i a l 13 front-end interface STI5518 98/294 7170179 d irq atapi, irq1 3 address pins, cpu_adr[16:18] 16 data pins, cpu_data[0:15] 2 chip selects, cpu_adr[19:20] the following figure shows the block diagram of the atapi interface authentication the atapi drive requires authentication as a legal dvd drive. the authentication process carried out by both hardware and software. the hardware part in the css decryption block is accessed via register reads and writes from the st20. pio data transfer the emi is programmed by the st20 to the pio transfer speed that is supported by the drive. the atapi drives (dvd drive and hdd) support different transfer speeds. speeds up to and including mode 4 are supported by the STI5518 if the css decryption unit is not used. 13.6 i 2 s interface introduction the STI5518 supports dvd drives with an i 2 s interface. a hardware sector processor is associated to the interface. formats accepted on this input are given in the sector processor (sp) and are described below. figure 41 atapi interface block diagram 3.3v transceiver diow dior ata-2 drive da0-2 atapi irq 2 dd0-15 cs0-1 STI5518 cpu_data[0:15] atapi_wr(pin188) atapi_rd(pin187) 3 cpu_adr[19:20] cpu_adr[16:18] irq1 dir oe cpu_ce[1] cpu_r/w
c o n f i d e n t i a l STI5518 13 front-end interface 7170179 d 99/294 sector processor the sector processor (sp) only accepts data from the serial interface. the activities of the sector processor are: sector capturing (dvd, vcd, cdda) subcode capturing (vcd, cdda) sector filtering (dvd) sector header bytes strip off (dvd, vcd) flywheel subcode error correction serial to parallel conversion for data and subcodes selectable error strategy for received sectors indication of navigation pack reception (dvd) the main function of the sector processor is to allow the user to filter and capture groups of contiguous dvd sectors by programming the first and last sector numbers of a group. this mechanism is used to ensure only the dvd required sectors reach the track buffer. in normal, the use of the sector processor implies having the track buffer in STI5518 memory space (memory savings). the sector header information is also stripped and stored. it can be read by the microprocessor via a number of user registers (useful information for decryption). the resulting sector payload is then sent to the dma engine via the decryption engine. the sector processor also indicates via an interrupt when a navigation pack is received in the sector stream. using these capture and filter functions, the overspeed processing function in dvd can be realized. in cd-da mode the sector processor uses the subcode information it receives to ? sectorize ? the data thus allowing overspeed processing to be handled for these backward compatible modes. since there is no general configuration register the user must configure each of the three modes dvd, vcd, cd-da separately. in dvd mode the sector processor expects a sectorized serial bit stream according to the dvd format ( figure 42 and figure 43 ). the b_sync signal indicates the start of each sector. erroneous sectors are flagged by the b_flag signal at the last byte of the sector (crc check is done by the front end). whenever a captured sector is flagged erroneous, an interrupt is given to the st20. depending on the error strategy (se_emr_erro mode register) the following will happen: 1 the last stored sector is removed and the sector processor waits for a new arrival of this erroneous sector (the st- 20 is expected to issue a seek command). 2 the last stored sector is not removed and capturing continues with the next sector. start/stop capturing is checked on a 3 bytes sector address in the sector address. the 2048 bytes of user data are stored after decryption in the track buffer through dma. when a navigation pack enters the sector processor, it is signaled to the st-20 by means of an interrupt (nprenav). in vcd mode the sector processor receives a sectorized serial bit-stream according to the cdrom-xa format. in this mode the b_sync signal is not valid as a sector sync. sector synchronization is obtained by detecting the 12 bytes cdrom sector sync (00 ff ff ff ff ff ff ff ff ff ff 00) in the i 2 s data. before interpreting, the sector data is
c o n f i d e n t i a l 13 front-end interface STI5518 100/294 7170179 d descrambled. erroneous bytes are flagged by the b_flag signal. whenever a captured sector contains erroneous bytes, an interrupt (rderr) is given to the st-20 and the behavior will be as described above in dvd mode. after descrambling, start/stop is checked on a 3 byte sector address in msf (minutes seconds frames) format in the header (see figure 46 ). from the real-time sectors, only the sectors containing video and audio (indicated by bits a set or v set of the sub mode byte in the sub header) are stored into the track buffer (see figure 47 ). also interrupts are given if certain types of sectors enter the sector processor (sub header-sub mode byte, bits eof, eor or t set). since the sub header is present twice in a sector, some error strategy is implemented. if one of the 2 is erroneous, the error flag is suppressed and the right one is taken. if both are erroneous a rderr interrupt will be given. set the se_mod register to capture static (file system) sectors (mode 2 form 1). the complete sector, excluding sector sync is stored into the track buffer. thus enabling the st-20 to carry out error correction if needed. error correction is not done by the sector processor. in the case of real-time data (mode 2 form 2), only sectors which contain audio and video data (indicated by the submode bytes) are sent to the dma engine (see figure 47 ). in cdda mode the sector processor receives a serial bitstream of audio samples. start/stop and overspeed control is done by means of the absolute time coded within q-channel of subcode. the subcode has a fixed relation to the serial bitstream of audio samples enabling the sector processor to split up the cd-da data stream in ? sectors ? of 2352 bytes.the sector processor uses a flywheel for absolute time, which is set according incoming subcode, but increments if the subcode is erroneous (crc check). this allows to start/stop capturing, even if the subcode of the start/stop sector is erroneous.the subcode is available on pin b_v4. figure 42 dvd data sector structure figure 43 dvd data sector identifier 172 bytes 4 bytes 2 bytes 6 bytes id ied cpr_mai main data 160 bytes (d0 ~ d159) main data 172 bytes (d160 ~ d331) main data 172 bytes (d332 ~ d503) main data 172 bytes (d1708 ~ d1879) main data 168 bytes (d1888 ~ d2047) edc 4 bytes 12 rows id ied cpr_mai main data 160 bytes (d0~d159) main data 172 bytes (d160~d331) main data 160 bytes (d332~d503) main data 160 bytes (d1708~d1879) main data 160 bytes (d1888~d2047) edc b31 b24 b23 b0 sector information sector number
c o n f i d e n t i a l STI5518 13 front-end interface 7170179 d 101/294 as with vcd the subcode information is stored into the sub code buffer. figure 44 vcd sector format (mode 2 form 1) figure 45 vcd sector format (mode 2 form 2) figure 46 vcd header and sub header format figure 47 vcd submode byte format figure 48 cd-da sector format sync header sub header user data edc ecc 12 4 8 2048 4 276 data stored in track buffer sync user data sub header header edc 12 4 8 2324 4 data stored in track buffer minutes seconds frames mode header file number channel number sub header submode coding info file number channel number submode coding info end of record (oer) video (v) audio (a) data (d) trigger (t) form (f) real time sector (rt) end of file (eof) 7 6 543210 audio samples audio samples audio samples data stored in track buffer 2352 2352 2352 data stored in track buffer data stored in track buffer
c o n f i d e n t i a l 13 front-end interface STI5518 102/294 7170179 d v4 interface the v4 interface is used in cd-da and vcd modes to transfer subcode information. the format on b_v4 pin is similar to the rs232. signals the table below details i 2 s interface pins. the inter-ic sound (i 2 s) bus was initially a serial link for digital audio. it has been extended to vcd and dvd. figure 49 cd-da subcode format figure 50 subcode format and timing at b_v4 pin pin n name type function 16 b_data i i 2 s data 17 b_bclk i i 2 s bit clock 18 b_flag i error flag 19 b_sync i sector sync/abs time sync 20 b_wclk i i 2 s word clock table 51 i 2 s interface pins pqrstuv wqrstuv pwqrstuv p w 96 bytes - p ? subchannel:signalswithaflagwheremusicordatastartonatrack ? - q ? subchannel:containstimeinformation ? control address data abs minute abs second abs frame crc 4 bits 48 bits 4 bits 24 bits 16 bits - r-w ? subchannels:containgraphicinformation ? 24 words 96 x 6 bits 24 words 24 words 24 words t sync 1 q1 r1 s1 t1 u1 v1 w1 t bit 1 q2 t gap w96
c o n f i d e n t i a l STI5518 13 front-end interface 7170179 d 103/294 the following four figures illustrate the different i2s modes supported. figure 51 i 2 s bus data format (16-bit word length) figure 52 i 2 s bus data format (24-bit word length) figure 53 i 2 s bus data format (32-bit word length) figure 54 i 2 s bus data format (variable word length) b_bclk b_data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d1 d0 flag-msb (1 is unreliable) flag-lsb flag-msb b_flag b_wclk right left b_sync d15 d14 d2 b_bclk b_data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d1 d0 flag-msb (1 is unreliable) flag-lsb flag-msb b_flag b_wclk right left b_sync d15 d14 d2 b_bclk b_data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d1 d0 flag-msb (1 is unreliable) flag-lsb flag-msb b_flag b_wclk right left b_sync d15 d14 d2 b_data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d1 d0 flag-msb (1 is unreliable) flag-lsb flag-msb b_flag b_wclk right left b_sync d15 d14 d2 b_bclk variable number of clocks
c o n f i d e n t i a l 13 front-end interface STI5518 104/294 7170179 d 13.7 decryption cell the decryption cell provides all the necessary logic to decrypt dvd data as well as perform the transformations required for authentication. all necessary keys are internally coded and unreadable externally. data decryption is performed by the cell after the st20 has read, from the sector header information registers (in the sector processor) the title keys and written them into the decryption cell via the key load register. after a hard reset, the decryption is in reset mode (fei_gcf[7] is set). the decryption cell is able to handle automatically encrypted or non-encrypted sectors. before initialization, the decryption needs to be bypassed (fei_gcf[5]).
c o n f i d e n t i a l STI5518 14 link 7170179 d 105/294 14 link 14.1 introduction the link interface accepts a constrained dvb or dss transport stream input and extracts a packet elementary streams (pes) for decode and play. section streams are extracted from the bitstream and stored in buffers for use by the decoder control unit. a high-speed sdav (simplified digital audio video) interface transfers transport packets between the STI5518 and external units for recording or playback. this interface supports an external p1394 link layer controller. the link includes a national renewable security system (nrss) interface for external descrambling. the figure below illustrates the link architecture. 14.2 mpeg-2 & dss systems layers two layers are used to describe link interface processing: figure 55 link architecture parallel nrss interface st20 bus controller filter ram mux fei_gcf[0] mux mux mux fei_gcf[5] i 2 s serial interface fec interface dvd css decryption acquisition ram descrambler (reserved) transfer processor atapi sector processor dma sector processor transport processor link fei mux mux mux fei_gcf[12] fei_gcf[6] interface interface interface fei_atapi_cgf[1] fei_gcf[1] or fei_gcf[12] or fei_atapi_cgf[1]
c o n f i d e n t i a l 14 link STI5518 106/294 7170179 d transport packets (tp) layer, packetized elementary stream (pes) or sections (for program specific information) layers. the link interface performs a complete processing at the tp layer and possibly at pes or section layers. function dvb layer dss layer acquisition tp tp descrambling tp or pes tp h/w filtering (psi for dvb, ca for dss) section tp table 52
c o n f i d e n t i a l STI5518 14 link 7170179 d 107/294 14.3 overview the link connects the front-end interface to the mpeg decoders and the st20. it is composed of the following units, and the figure below shows the block diagram: acquisition ram (ar) + nrss interface descramblers (descr) sdav/p1394 interface filter ram processor units, including a transport processor, section processor and transfer processor adaptation field filtering clock recovery dma engine figure 56 link block diagram nrss i/f acquisition ram (64 bytes) dvb-dss fec serial input or dvd-css decryption output nrss input nrss output external descrambler fifo 20 bytes fifo 64 bytes link i/f data bus (7:0) frc fram 480x32 bytes fifo 16 bytes af filtering command lines address decoder link interface dma sdav splitter st20 data bus (31:0) link i/f registers transport processor section processor transfer processor descrambler sdav interface sdav/p1394 interface input/output
c o n f i d e n t i a l 14 link STI5518 108/294 7170179 d input interface (acquisition ram + nrss) signals at the front-end interface and link interface are asynchronous. data received from the front-end interface and provided by the serial-parallel converter, are buffered in the acquisition ram (ar), which is a fifo memory. the packet processing must start before the watchdog signal is activated (at least a few bytes before the ar is full). descrambling dvb and des descramblers are both implemented. for dvb, tp and pes level descrambling are supported. for dss the descrambling is only done at tp level only. up to 8 different key-sets can be used to descramble up to 32 streams. the descrambling keys are located in the fram and are automatically loaded after pid filtering. if the payload contained in an acquired tp is scrambled, the descrambler is set-up to handle descrambling and to return descrambled bytes. if the payload is not scrambled, the payload bytes are sent directly. note the descrambler is not used for dvd applications. sdav/p1394 interface the high-speed sdav/p1394 digital interface transfers either scrambled or non-scrambled transport packets between the STI5518 and an external unit, for recording or playback. the simplified digital a/v bus is a point-to-point connection. it only allows one source on any bus segment at a time. the ieee1934 standard provides a single i/o interface with a simple connector that can handle numerous devices through a single port. this block sends a single stream out to a high-speed serial digital bus, or plays back a stream from that bus. sdav and ieee1394 bus formats are supported. pid filtering this block contains a filter to receive the tp of one program. it extracts the transport packets of up to 32 streams from the incoming bitstream. note pid filtering is not used for dvd applications. section filtering a second filter function is applied to all section-type data. the section header can be compared to up-to 32 targets for each stream. the maximum length of the targets is 16 bytes for dss and 14 bytes for dvb. each bit of each target can be masked individually. for one target byte, two bytes of ram are required. the total number of target bytes is defined by the size of the filter ram array. note section filtering is not used for dvd applications. adaptation field filtering adaption field filtering extracts pcr information, or discards any undesired data contained in the extracted tp. note adaption field filtering is not used for dvd applications. processor units and dma the transport processor handles the tp-layer relevant bytes, the section processor handles the section-layer relevant bytes and the transfer processor counts the transferred bytes or discards unwanted data. the dma engine handles the transfer or relevant bytes to the appropriate st20 memory buffer.
c o n f i d e n t i a l STI5518 14 link 7170179 d 109/294 14.4 detailed description 14.4.1 input interface the link interface receives the tp through the input interface section; it is a fully asynchronous fifo buffer (64bytes) that decouples write and read clocks. data are latched on the falling edge of fec_b_clk. the fec_p_clk is active-high during the significant bits of the packet (188 x 8 for dvb, 130x8 for dss). on this pin, the rising edge is detected and the internal fifo counter is reset. the fec_error signal should be active high for an entire packet if there is an error somewhere in the packet. these packets will not be written into the ar. this signal should only transition at the rising edge of fec_p_clk. the maximum input data rate (fec_b_clk) is 59.5mbit/s or 7.43mbytes/s (7/8 of 68mbit/s). the internal link interface block data rate is 60mbits.t 14.4.2 nrss interface the figure below shows the nrss interface block diagram. the incoming signal comes from the sdav/p interface for dvb applications, or from the dvd-fei for dvd applications. this signal is transferred through the nrss interface to an external descrambler, after descrambling the signal is transferred back over the nrss interface to the nrss input. the descrambled signal is then moved into the acquisition ram. in dvb applications, the signal can bypass the nrss interface and pass from the sdav interface to the acquisition ram. the data can pass through without going out to the nrss. clocks description value sys_clk descrambler clock 60 mhz fec_b_clk bit clock signal up to 59.5 mhz table 53 link interface data rates figure 57 nrss interface block diagram 1 fec i/f 2 sdav i/f tape in nrss in 0 1 nrss mode 0 1 nrss mode or sdav_mode 0 1 sdav mode nrss out acquisition ram 3 s/p s/p s/p p/s s/p: serial parallel conversion p/s: parallel serial conversion
c o n f i d e n t i a l 14 link STI5518 110/294 7170179 d the following paths are used: two mux controls select whether the input is comes from the fec interface or a reserved input, and whether the nrss is used or not. the other fec signals pass through this block to ensure that proper timing is maintained. serial/parallel conversion is performed after nrss. register lnk_mode sets msb or lsb first in the serial-parallel converter. when the input is fec, the nrss_clk coming from the link interface is discontinuous. consequently, the data has to be maintained at the end of each byte. the nrss block inputs are shifted from a serial bit-stream into a serial-to-parallel converter shift-register, using the incoming clock, fec_b_clk. the parallel byte is then loaded into a register and a single bit is generated that toggles on each new byte. that signal is then sampled with the sys_clk. this asynchronous sampling takes a couple of clock cycles. the byte is then loaded into the output shift register for the nrss interface and is shifted out using the sys_clk. if the sys_clk is faster t han the incoming clock then there will be sys_clk cycles where there is no data available to shift out. when there is no available data, the nrss_clk output is forced to remain low for that clock cycle. this mechanism can be broken by making the fec clock (fec_b_clk) faster than sys_clk. normally the acquisition ram has all four of the fec input signals (fec_b_clk, fec_data, fec_p_clock, and fec_error). since the nrss interface has only clock and data, there is no indication of the beginning of a packet. within the nrss interface the link interface looks for a synchronization byte (0x47) coming from the nrss card to indicate the beginning of a packet and uses that to generate a packet clock. acquisition ram size the internal fifo counter is reset by the rising edge of the packet clock signal in dvb/dss mode, or by the rising edge of sector start in dvd mode. fec -> aram fec -> nrss -> aram sdav aram sdav nrss aram figure 58 serial input i/f from channel ic or link ic fec_b_clk fec_data fec_p_clk fec_error burst transmission bit 1 bit 2 bit n-1 bit3 bit n bit 1 bit 2 bit n-1 bit3 bit n micro is activating output z z z z burst transmission
c o n f i d e n t i a l STI5518 14 link 7170179 d 111/294 when the following packet arrives, the last bytes of the packet in process have to be read. to ensure this, the upper limit of this fifo is programmable by software so that the last byte of a packet is written as high as possible in the fifo, as shown in the figure below. the optimal acquisition ram size for each mode is as follows: dss mode = 44 (2*44 + 42 = 130) dvb mode = 63 (2*63 + 62 = 188) dvd mode if sector size is 2066 = 53 (38*53 + 52 = 2066) cd mode if sector size is 2048 = 58 (43*58 + 54 = 2548) 14.4.3 descrambler the figure below shows the tp and pes header format. the link interface contains two descramblers conforming to the dvb/des descrambler specifications. byte # 1 is the 1st byte of the tp - bit(7) = msb descrambler dvb. figure 59 acquisition ram figure 60 tp & pes headers 1st byte of a packet fifo (64 bytes) last byte dss = 42 last byte dvb = 62 bytes 1 to 44 (44) bytes 45 to 88 (44) bytes 89 to 130 (42) bytes 1 to 63 (63) bytes 64 to 126 (63) bytes 127 to 188 (62) upper limit = 44 upper limit = 63 0x47 byte 1/188 scrambling tp level sync_byte playload_unit_start_indicator (byte 6) pid (13 bytes) scrambling control - bytes (7:6) (scrambling + odd/even) af control bytes (5:4) cc bytes (3:0) playload 184 bytes scrambled at tp level if scrambling control(1) = 1 1 9+n n 23456789101112 13 ... pes header payload pes header length scrambling pes level scrambling control bytes (5:4) scrambled at pes level if scrambling control(1) = 1
c o n f i d e n t i a l 14 link STI5518 112/294 7170179 d the scrambling algorithm operates on the payload of a tp in the case of ts-level scrambling. a structuring of pes packets is used to implement pes-level scrambling with the same scrambling algorithm. the scrambling of mpeg-2 sections is at tp level. pes-level scrambling the pes data format is shown in the figure below. the following recommendations must be followed for pes-level scrambling. 1 the pes packet header must not be scrambled. 2 the header of a scrambled packet must not span multiple tp. 3 the tp containing parts of a scrambled pes packet should not contain an adaptation field (with the exception of the tp containing the end of the pes packet). 4 the tp carrying the start of a scrambled pes packet must be filled by the pes header and the first part of the pes payload. in this way, the first part of the pes packet payload is scrambled exactly as a tp with a similar payload. the remaining part of the pes packet payload is split in super-blocks of 184 bytes. each block is scrambled exactly as a tp payload of 184 bytes. 5 the end of the pes packet payload is aligned with the end of the tp by inserting an adaptation field of suitable size (as required in iso/iec 13818-1). if the length of a packet is not a multiple of 184 bytes, the last part of the pes packet payload (from 1 to 183) is scrambled exactly as a tp with a similar payload. scrambling control bits msb lsb (if msb = 1) dvb tp level byte # 4 bits(7:6) 1: scrambled 0: non-scrambled 1: odd key 0: even key dvb pes level byte # 11 bits(5:4) 1: scrambled 0: non-scrambled 1: odd key 0: even key dss byte # 1 bits(5:4) 1: non-scrambled 0: scrambled 1: odd key 0: even key table 54 figure 61 pes data format pes header pes data (scrambled) pes header pes data pes data af pes data ts packets
c o n f i d e n t i a l STI5518 14 link 7170179 d 113/294 14.4.4 sdav/p1394 interface the sdav/p1394 interface carries a single stream out to a high-speed serial digital bus, or plays back a stream from that bus. sdav and i eee1394 bus formats are supported, this section describes each format. sdav bus format this format uses a 49.152 mhz bit-rate in a non-return-to-zero (nrz) encoding method. the following signals are used: the signals strobe_tx and data_tx are reversed for transmit and receive, i.e. the signal strobe_tx acts as the data signal in receive mode and the strobe in transmit mode, the data_tx signal acts as the strobe signal in receive mode and data in transmit mode. the signal direction controls the mode; when direction is high, the mode is transmit and the other two signals are outputs. the time stamp, which is used to maintain proper packet placement, is the value of the lsb ? s of a continuously running 27 mhz clock. this time stamp is added for sdav bus and optionally for 1394 bus in tape-out mode, but it is simply discarded when received from these busses in tape-in mode. for sdav, during packet transmission, there is only a single mode transmitting on the bus so the media can operate in a half-duplex mode using two signals: data_tx/rx and strobe_tx/rx. nrz.data is transmitted on data_tx/rx and is a accompanied by the strobe_tx/rx signal, which changes state whenever two consecutive nrz bits are the same. this ensures that a transition occurs on either data_tx/rx or strobe_tx/rx for each bit. a clock with transition on each bit-period is derived from the exclusive-or of data_tx/rx with strobe_tx/rx as show below. signal direction pin name pin number pin direction sdav direction sdav description in sdav_data 103 i/o i strobe_rx (49.1 mhz) (nrz decoding) (only header + playload) sdav_clk 22 i/o i data_rx (nrz decoding) sdav_dir 104 i/o o direction (tape in) out sdav_data 103 i/o o data_tx (nrz encoding) sdav_clk 22 i/o o strobe_tx (49.1 mhz) (nrz encoding) (only header + payload) sdav_dir 104 i/o o direction (tape out) table 55 sdav bus format on the sdav/p1394 interface figure 62 format for dss and dvb in sdav mode figure 63 data_strobe nrz encoding (inside STI5518) 12 bits reserved 20 bits time stamp 130 bytes dss packet 10 bytes stuffing 12 bits reserved 20 bits time stamp 188 bytes dvb packet d q d q q data_tx strobe_tx data clock
c o n f i d e n t i a l 14 link STI5518 114/294 7170179 d packets are synchronized by introducing a clock ? gap ? of 16 clock (49.152 mhz) cycles (= clock stopped in figure 63 and figure 64 ). so if such a gap is detected, then the packet is finished. the following edge of the clock indicates the beginning of a new packet. p1394 bus format this mode uses the STI5518 in conjunction with an external 1394 link layer circuit to interface to the physical bus. the following signals are used. all three signals are outputs for tape-out mode, and inputs for tape-in mode. the clock is continuous and the data_ valid signal is active for the entire packet, without gaps between the bytes. the data_valid signal defines the size of the packet. the rising edge of data_valid determines the start of the packet. as for sdav mode, a clock ? gap ? of 16 clock cycles (up to 60 mhz) is needed before the next rising edge of data_valid. figure 64 data_strobe nrz decoding (inside STI5518) signal direction pin name pin number pin direction sdav direction sdav description in sdav_data 103 i/o i data_in (no nrz decoding) sdav_clk 22 i/o i clock_in continuous (up to 60 mhz) sdav_dir 104 i/o i data_valid_in (packet clock) out sdav_data 103 i/o o data_out (no nrz encoding) sdav_clk 22 i/o o clock continuous (60 mhz) sdav_dir 104 i/o o data_valid_out (packet clock) table 56 sdav bus format on the sdav/p1394 interface figure 65 format for dss and dvb in 1394 mode d q d q q data_1 (rising edge of clock) data_0 (falling edge of clock) data_rx strobe_rx clock = data_rx + strobe_rx 12 bits reserved 20 bits time stamp 130 bytes dss packet 10 bytes stuffing 12 bits reserved 20 bits time stamp 188 bytes dvb packet optional optional optional
c o n f i d e n t i a l STI5518 14 link 7170179 d 115/294 if the rising edge is asserted before this period has passed, the behavior is undefined. header if sdav or (1394 and header_enable) and not(pcm or dvd). padding if incomplete dma and not(pcm or dvd). stuffing if dss and (sdav or (1394 and header_enable). data path the maximum input rate is about 7.5mbytes/s (7/8 * 68mbits/s). the data are sent to the sdav interface either scrambled or not. note that the descrambler works up to 60mbits/s. null packets are not transmitted to the digital bus. packets concerning other programs, and any useless information are discarded. in such cases, packets may be generated by the st20 and transmitted by dma transfer for example. those packets must be isochronous with the packets extracted from the original multiplex. some tables(pat, pmt) may be modified by s/w to create new program guides for use in playback mode tape-in in tape-in mode the sdav interface serves as a data source similar to, and instead of, the fec input. the data is received from the interface and sent to the nrss block and into the acquisition ram. the data can be sent directly or re-synchronized to sys_clk. figure 66 timings in p1394 mode bus mode incomplete dma header_ enable stuffing_ enable header bytes tp bytes padding bytes stuffing bytes total sdav dvb 0 x x 4 188 192 sdav dvb 1 x x 4 x 188-x 192 sdav dss 0 x x 4 130 10 144 sdav dss 1 x x 4 y 130-y 10 144 1394 dvb 0 0 x 188 188 1394 dvb 0 1 x 4 188 192 1394 dvb 1 0 x x 188-x 188 1394 dvb 1 1 x 4 x 188-x 192 1394 dss 0 0 0 130 130 1394 dss 0 0 1 130 10 140 1394 dss 0 1 0 4 130 134 1394 dss 0 1 1 4 130 10 144 1394 dss 1 0 0 y 130-y 130 1394 dss 1 0 1 y 130-y 10 140 1394 dss 1 1 0 4 y 130-y 134 1394 dss 1 1 1 4 y 130-y 10 144 table 57 clock_in/out data_in/out datavalid_in/out
c o n f i d e n t i a l 14 link STI5518 116/294 7170179 d any header or stuffing, if enabled, are stripped from the packet and discarded with the exception of the 12 reserved bits in the header. these reserved bits are latched in the register lnk_extra_bits. if these bits differ from the contents of the register prior to the latching, an interrupt is generated. the sdav_overflow interrupt is generated to indicate to the st20 that some extra_bits are available. both fields (sdav_overflow and sdav_underflow) are set in the lnk_stat_fifo. this irq can be masked by register bit lnk_extra_bits[0], and is generated only when the incoming extra_bits changes value. tape-out in tape-out mode, the sdav block receives data from the acquisition ram, or from the descrambler. the link i/f system clock (sys_clk) is used as clk_in (60 mhz). the output clock is the interface clock (49.1 for sdav, up to 60 mhz for 1394). the input data stream speed varies with the speed of the incoming fec data, or it will be at whatever speed the dma engine can provide. the data are latched (at the clk_in frequency) into a single port ram to guarantee the output of one complete packet at the corresponding clock frequency. this means that the sdav block will receive about one byte every 8 clock cycles (clk_in). as soon as there is enough information in the ram (not to run out of data before the end of the packet), the sdav i/f generates the header information and then converts the data to the sdav bus serial format. cpu generated packets the cpu can create custom program guide packets for insertion into the bitstream and dma the packets to the sdav block. the packets are inserted into the out-going stream where possible. the dma is set-up to send 32-bit word data to the sdav block. before enabling the dma, the st20 must set the value of the lnk_sdav_dma_en register bits first_byte_posit and last_byte_posit. first_byte_posit should be loaded with the 2 lsb of the address of the first byte to be transferred. last_byte_posit should be loaded with the 2 lsb of the address of the last byte to be transferred. if the data that is being sent starts at address 0x40001000 and ends at address 400010ff, the value of first_byte_posit is 00 and the value of last_byte_posit is 0x11. if the data to be sent starts on an odd boundary such as 0x40001001, the dma should start with the address 0x40001000 but the first_byte_posit should be loaded with 01. similarly, if the data to be sent ends on an odd boundary such as 0x400010fe, the dma should transfer the entire 32 bit word starting at address 0x400010fc but the last_byte_posit should be loaded with 10. 14.4.5 fram introduction the fram is a dual port 480 x 32 bit ram that holds all of the link interface information. this includes the filter information, the stream configurations, descrambler keys and the irq words. one port is used by the micro to initialize the ram. the other port is used by the processor, the filter and the descrambler. sdav input sdav output sdav_overflow extra_bits_irq sdav_overflow sdav_underflow when both = 1 sdav_underflow table 58
c o n f i d e n t i a l STI5518 14 link 7170179 d 117/294 after the pid is filtered, the stream number is used to generate the address for the stream initialization. this configuration determines how stream is processed (section, error code, filtering...). for power reduction, the fram is only enabled when an access from one of the processors occurs. this happens in case of pid filtering, af filtering, section filtering, the loading of the stream configuration, the saving of the stream configuration at the end of the packet (section length if section is over 2 tp, cc...) and the irq status word read and write operations. filtering filtering is done by pre-calculating the result. the byte to be filtered generates the address in the fram. a ? 1 ? at an address means a match. for a 8 bit value, this would give 256 bits in the ram. to reduce the ram size, filtering is done in four steps per incoming byte. in each step, 2 bits of the incoming byte plus a 2-bit pointer, generate the address in the ram. this gives a 16-bit ram for one filter byte. each bit of the byte to be filtered can be masked individually as described below. because the ram is 32 bits wide, 32 targets can be filtered in parallel. however, it is also possible to filter on less then 32 targets. in this case the mux at the output of the fram allows selection of only a part of the data. with each new byte to be filtered, the address of this mux changes (by adding the filter number) and selects a different part of the output data. therefore, the lower bit of the filter match register holds the result of the filter process. for example, if only one target is filtered, the lsb of the register holds the result. figure 67 first and last bytes for dma transfer to the sdav interface [31:24] [23:16] [15:8] [7:0] first byte first_byte_posit (sdav_dma_en register) valid 11 valid valid 10 valid valid 01 valid valid valid 01 valid valid [31:24] [23:16] [15:8] [7:0] last byte last_byte_posit (sdav_dma_en register) valid 00 valid valid 01 valid valid 10 valid valid valid 11 valid valid
c o n f i d e n t i a l 14 link STI5518 118/294 7170179 d error procedures the following error mechanisms are applied. the cc error code insertion can be switched on or off for each stream individually, by the stream configuration. figure 68 fram organization filter mask value in fram filter mask value in fram 01101100 11111111 0100 0010 0001 1000 ... 01101100 11111110 0100 0010 0001 1100 01101100 00000010 1111 1111 1111 1100 01101100 11111101 0100 0010 0001 1010 01101100 00000001 1111 1111 1111 1010 ... 01101100 00000000 1111 1111 1111 1111 all input bytes are valid table 59 error filtering examples error mode description fec dvb dss this signal is delivered by the link_ic and signals a packet error. in this case the transport packet is not processed, it is not written into the ar. sync_byte dvb if the sync_byte in the packet header is not correct (!= 0x47), the tp is rejected. transport_error _indicator dvb this bit belongs to the tp header; if it is set the tp is rejected. this is done with the filter process. cc dvb, dss if the received cc does not match the expected one, different mechanisms are applied according to the stream type. table60error mechanisms event action suspend = ? 0 ? no cc error generated table 61 cc error code pid filtering (32 x 32 bit) key memory (32 x 32 bit) for up to eight scrambled streams stream configuration #1 (32 x 32 bit) stream configuration #2 (32 x 32 bit) stream configuration #3 (32 x 32 bit) irq registers (32 x 32 bit) section filtering (288 x 32 bit ) 0x000 0x020 0x140 0x160 0x180 0x1a0 0x1c0 32 bit uc bus ram array (480 x 32 bit ) 32 bit to f_ram cntrl .
c o n f i d e n t i a l STI5518 14 link 7170179 d 119/294 the following table summarizes the cc processing for dvb. 1 this will create a cc error for the next packet on this pid. 2 if discontinuity_indicator is set (in the af) and if an error code was inserted, this code must be removed. not equal filtering the not equal filtering mode can be used only in dvb, not in dss. this mode filters on a not-equal condition (defined in register stream_conf_1). the byte to which this is applied is programmable. this filtering can also be done in parallel, on up-to 8 different targets. when using this function, one additional byte has to be filtered after the ? not-equal ? byte. after the section length, register lnk_stream_conf_1 bit sec_f_inv is loaded. it cannot be loaded with ? 111 ? . the function is activated by register lnk_stream_conf_1 bit sec_f_inv. cc error and error_patt = ? 1 ? and not (only af) and pes error code is generated: b4 00 00 01 b4 cc error for a section stream if section is active, the stream is disabled and irq is generated (see below) af payload event link i/f processing 0 0 cc is incremented or not - skipped tp: dummy xfer 1 0 cc n cc n-1- cc n 1 cc n-1 - end of cc processing - ccstored is modified by the link i/f (1) 0 1 cc is incremented cc n cc n-1- cc is not incremented - end of cc processing - duplicated tp: dummy xfer - section + suspend = 1: stream disabled (2) - section + suspend = 0: nothing - pes + suspend = 1: insert error code - pes + suspend = 0: nothing 1 1 same processing as previous combination (2) table 62 cc processing for dvb figure 69 basic principle of filter mechanism table 61 cc error code 255 0 ............................. f byte (8 bit) in this case the filter byte gives direct the address in the ram array. ram array of 256 x 1 for each filtered byte result
c o n f i d e n t i a l 14 link STI5518 120/294 7170179 d one byte of each target can be checked to be different from a specific value. at the beginning, all sections can be received. this is done by masking the specified byte (the fram is initialized with 00h in not_equal mode). after each section has arrived, the filter for the specified byte can be written into the fram (see table 63 ). note 0: bit is masked, 1: bit is not masked 14.4.6 dma mpeg audio, video and system data can be transferred to any location in the st20 address space (internal sram, external sdram or dram, mpeg decoders) via a dma controller. the dma transfers the data from the link interface to a destination address which can be set individually for each stream. figure 70 section filtering example filter mask value in fram equal mode not-equal mode 01101100 11111111 0100 0010 0001 1000 01101100 valid all valid except 01101100 01101100 01101100 0100 0010 0001 1100 01101100 and01101101 valid all valid except 01101100 and 01101101 01101100 10011111 1100 1010 0001 1010 01101100 and 00101100 and 01001100 and 00001100 valid all valid except 01101100 and 00101100 and 01001100 and 00001100 valid ... ... ... ... 01101100 00000000 1111 1111 1111 1111 all bytes valid no byte valid 01101100 0000 0000 0000 0000at least 1 nibble = 0000 no byte valid all bytes valid table 63 equal and not-equal filtering table_id section_length not equal mode available for one of these 6 bytes 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 100 011 010 001 000 sec_f_inv sec_f_count = 100 (from stream_conf_1) not equal mode result available (1 byte later) these bytes can be written into the fifo (16 bytes). this means that up to 14 bytes (max filter length) can be filtered.
c o n f i d e n t i a l STI5518 14 link 7170179 d 121/294 dma configuration the figure below shows the dma address configuration, the following table gives the dma configuration registers. dma description at the beginning of the packet, the dma is initialized by registers lnk_stream_conf_2 and lnk_stream_conf_3. there are two basic dma modes: incremental (circular and linear) and non incremental. at the end of the packet, the current dma address can be stored back to the fram. this is reloaded by the link interface when the next packet on this stream arrives. address write-back is not performed in dvd mode. if register lnk_stream_conf_2 bit increment is set to ? 1 ? , and register lnk_mode bit dfb is set to ? 0 ? , the last transfer will be a burst transfer, where unused bytes are filled with dummy data. if register lnk_stream_conf_2 bit increment is set to ? 0 ? , or register lnk_mode bit dfb is set to ? 1 ? , the exact number of bytes is transferred (mpeg decoders). the address counter keeps the value of the last valid byte that is transferred. two buffers are used in the dma (two times 4x32 bits). while one buffer is transferred, the second one is filled. this allows data to be read from the link interface even if the dma has to wait for the st20 bus. the address pointer, which is normally increment every time something is transferred, must be limited in order not to destroy information from other buffers or program code. therefore, circular buffers are implemented. circular buffer (incremental mode) to stop the transfer when the circular buffer is full, the cpu writes the stop_address in the link interface. in this case, when the transfer pointer (start_address) reaches this value, the dma is aborted. this prevents overwriting of data which has not been processed. the cpu updates the stop_address each time it has finished processing data. a start_address(2:0) and a stop_address(9:0) are specified. the meaning of these bits depends on the buffer_size(2:0). the following figure illustrates how the buffer-size is defined. table 64 dma address register bits circular buffer lnk_stream_conf_2 buffer_size 26:24 circular buffer size stop_address 23:14 dma_stop_address(14:5) to (7:0) start_address 13:11 dma_start_address(14:12) to (7:5) dma_bank_addr 10:7 dma_address(31:28) dma_high_addr 6:0 dma_address(21:15) lnk_stream_conf_3 dma_low_addr 26:12 dma_address(14:0) table 65 dma configuration registers 31 28 21 14 10 63 0 dma_bank_address[3:0] dma_high_address[6:0] current_address[14:0] address stored in fram
c o n f i d e n t i a l 14 link STI5518 122/294 7170179 d figure 71 buffer_size definition buffer_size size 000 256 bytes base address 0 0 0 0 0 0 0 0 start base address current base address stop end base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dma_bank_addr not used dma_high_addr current_address = first byte to be written stop_address = last byte read 00000 11111111 start_address stop_address buffer_size size 001 512 bytes base address 00000000 start base address current base address stop end base address 00000 1111111 1 s1 s1 + 1 buffer_size size 010 1024 bytes base 00000000 start base current base stop end base 00000 1111111 1 s2 s1 s2s1 + 11 buffer_size size 011 1536 bytes base 00000000 start base current base stop end base 00000 1111111 1 s3 s2 s1 s3s2s1 + 101 start current stop end start current stop end start current stop end start current stop end base base base base base base base base base base base base base base base base buffer_size size 100 2048 bytes buffer_size size 101 3072 bytes buffer_size size 110 4608 bytes buffer_size size 111 8192 bytes 0000000 0 00000 1111111 1 s3 s2 s1 s3s2s1 + 111 0000000 0 00000 1111111 1 s4 s3 s2 s1 s4s3s2s1 + 1011 0000000 0 00000 1111111 1 s5s4 s3 s2 s1 s5s4s3s2s1 + 10001 0000000 0 00000 1111111 1 s5s4 s3 s2 s1 s5s4s3s2s1 + 11111 end address = start_address + 256-1
c o n f i d e n t i a l STI5518 14 link 7170179 d 123/294 when the transfer address reaches the top of the circular buffer, it is reset to the bottom of the circular buffer and the transfer continues. the figure below illustrates the circular buffer operation. if the transfer is aborted (if stop_address is reached), the dma engine generates a dma overflow and the rest of the packet is discarded. the dma buffer is flushed to its destination, stream_conf_3 is saved back to the fram, and the stream is automatically disabled. the dma_overflow-bit is set, along with the stream_number in the status word. the status word is written into the lnk_stat_fifo register. dvd buffer (linear mode) in dvd mode, the dma can be incremental or non-incremental. if it is incremental, the circular buffer is not used. if register bit lnk_stream_conf_2.increment=1, the start address is set by register bit lnk_stream_conf_3.dma_low_addr, and is incremented after each access, independent of the start and stop addresses. if register lnk_stream_conf_2.increment=0, a ll of the data is written to the address specified by register bits lnk_stream_conf_2.dma_high_addr and lnk_stream_conf_3.dma_low_addr. non-incremental buffer this mode is used when addressing the cd fifos. the current_address(1:0) is incremented by ? 1 ? after each access. 14.4.7 clock recovery this block assists the control unit in the clock recovery and clock synchronization processes. it uses local counters clocked with the video clock (27 mhz). the counter values are latched in four registers that can be read by the control unit: pcr_ext, pcr and v_pts. lnk_pcr_ext(8:0) and lnk_pcr(31:0) are updated with the local time counters when a new packet occurs. if an af with pcr is found (if pcr flag is present in lnk_af byte #0), a sample of the 27 mhz clock is latched and the first 8 figure 72 circular buffer diagram circular buffer dvd buffer non-incremental buffer buffer_size not used stop_address not used start_address dma_bank_address used to initialize the dma dma_high_address dma_low_address table 66 non-incremental buffer start + size 1 1 stop(y:1) 0 0 ... ... dma_low(x:1) start(w:1) 0 0 ... 000 ... 00 0 start of tp
c o n f i d e n t i a l 14 link STI5518 124/294 7170179 d bytes of the incoming adaptation field are stored in lnk_af[1:0]. it allows the controller unit to synchronize the decoder clock reference (27 mhz). a new pcr can ? t be latched if the current pcr (af[1]) has not been read by the micro. the signal pcr_latch_en is set to indicate that a new pcr can be latched. lnk_v_pts (or lnk_a_pts) is updated with the local time counter(31:0) when a rising edge is detected on v_pts _latch (or a_pts_latch from the audio decoder or external ac3). the v_pts_latch and a_pts_latch are reset by the clock recovery entity after the register has been read by the control unit. a counter (19:0) is also required to generate the time stamp used for the sdav header. the time stamp value is updated at the beginning of each packet, as illustrated below. 14.4.8 interrupts there are nine interrupt sources for each stream. each interrupt source has a corresponding status bit in the register lnk_stat_fifo. if the interrupt is enabled (mask=1) and the corresponding status bit is set, an interrupt event is generated. successive interrupts generate successive status words (lnk_stat_fifo) that are stored in chronological order in a 32-word fifo. this is useful if multiple interrupts occur within a packet (multiple sections per packet). the fifo is implemented as a circular buffer in the fram. in the status-word, the stream-number field (lnk_stat_fifo.sn) and interrupt status bits are always applicable. the target-match (lnk_stat_fifo.tm) and other-match (lnk_stat_fifo.om) are only valid on end-of-filter (lnk_stat_fifo.eof) and incomplete-filter interrupts (lnk_stat_fifo.if). in addition, the filter_offset field is only valid on incomplete-filter interrupts. the lnk_stat register indicates whether interrupts are pending (fifo-not-empty, lnk_stat_fifo.fne). each time a status-word is written to (resp. read from) the fifo, a write (resp. read) pointer is incremented (lnk_stat). the fifo is read by the micro through the lnk_stat_fifo register. when a word is read, it is removed from the fifo. the st20 checks the lnk_stat (for fifo emptiness or overflow) prior to reading the lnk_stat_fifo. the st20 does not read the fifo if it is empty. when at least one status word is present in the lnk_stat_fifo, the interrupt line to the st20 is set active and kept active as long as the fifo is not empty. the interrupt line becomes inactive when the last word is read from the fifo. if the fifo is full and new interrupt events occur, no further status-word is written to the fifo and the fifo overflow bit (lnk_stat.fo) is set. this bit is reset when the st20 reads a word out of the fifo. figure 73 clock recovery counter (8:0) / 300 counter (31:0) lnk_pcr_ext counter (19:0) time_stam_reg lnk_pcr lnk_a_pts and 9 20 pcr_latch 32 pcr_latch_en (from af block) v_pts_latch a_pts_latch pcr_latch (pulse) packet_clock (from fec or sdav/p1394) lnk_v_pts
c o n f i d e n t i a l STI5518 14 link 7170179 d 125/294 the table below describes the interrupt sources. interrupt source description ar overflow status bit lnk_stat_fifo.ao not maskable, no stream disabling irq generation an ar overflow occurs if at least one of the following condition is true: a new packet has started to be stored in the ar, and its processing has not started as ? ar_timeout ? bytes have been stored; the write pointer of the ar reaches the read pointer. this can happen if the link interface hangs, or if the st20 bus traffic prevents data to be output fast enough. irq processing the stream is not disabled when such an ar overflow occurs, the current packet processing is aborted. all packet data which have not already been passed to the dma write-buffer are discarded. the dma write-buffer is flushed to its destination. an internal reset signal is generated to put the whole link interface into a state where it expects a new packet to arrive: if a start-of-packet is present in the ar, data input is not stopped and overwrites the discarded data; if a start-of-packet is already present in the ar, its processing starts immediately. the stream_conf_3 of the aborted packet is not saved back to fram. therefore, appropriate error processing will be performed due to cc discontinuity on the next packet of the same pid. the ar_overflow bit is set along with the stream_number in the status-word, and the status- word is written into the link_stat_fifo. dma overflow status bit lnk_stat_fifo.do not maskable, stream disabling possible. irq generation a dma_overflow interrupt occurs when the write-pointer of the dma transfer reaches the stop value stored in stream_conf_2. irq processing the stream is disabled. the rest of the packet is discarded. the dma buffer is flushed to its destination. stream_conf_3 is saved back to fram. the dma_overflow bit is set along with the stream_number in the status-word, and the status-word is written into the link_stat_fifo. table 67 interrupt sources
c o n f i d e n t i a l 14 link STI5518 126/294 7170179 d bad section status bit lnk_stat_fifo.bs not maskable, stream disabling possible. irq generation when saving a section to memory, the link interface counts the section length and detects the end of the section. the following conditions will generate a bad section interrupt: the pus of the current packet is set and the pointer_field at the beginning of the packet does not correspond to the number of remaining bytes in the currently transferred section. the cc of the current packet has the wrong value on a section packet when a section is being processed. the pus is not set and the bytes following the current section are not stuffing bytes (ff). irq processing the stream is disabled.in this case, the bad_sec bit is set along with the stream_number in the status-word, and the status-word is written into the link_stat_fifo.(note that the cc is checked on pes streams if the error_patt bit of the stream_conf_1 is set, but no irq is generated there.) end-of-section filtering status bit lnk_stat_fifo.eof maskable, no stream disabling. irq generation dss/dvb mode: an eof interrupt is generated if the eof_irq bit is set for the current stream and a filtering operation has been completed with a match. dvd mode: an eof interrupt is generated if the eof_irq bit is set for the stream 0 and the dma engine has been initialized with the parameters stored in fram. irq processing normal processing continues. dss/dvb mode: the eof_flag is set along with the stream_number in the status word. the values of target_match and other_match are stored in the status word which is pushed into the link_stat_fifo. this information can be useful for the application software. dvd mode: the eof_flag is set along with the stream_number in the status word. end-of-section transfer status bit lnk_stat_fifo.eos maskable, no stream disabling. irq generation dss/dvb mode: an eos interrupt is generated if the eos_irq bit is set for the current stream number and a section has been completely transferred by the dma controller to memory. dvd mode: an eos interrupt is generated if the eos_irq bit is set for the stream 0 and the dma engine has finished the transfer of a packet. irq processing normal processing continues. dss/dvb mode: the eos_flag is set along with the stream_number in the status word. the status word is written into the link_stat_fifo. dvd mode: the eos_flag is set along with the stream_number in the status word. interrupt source description table 67 interrupt sources
c o n f i d e n t i a l STI5518 14 link 7170179 d 127/294 incomplete filtering status bit lnk_stat_fifo.if maskable, no stream disabling. irq generation an incomplete filtering interrupt is generated if the incomplete_irq bit is set, a section filtering operation is not complete at the end of a packet and at least one temporary match is pending. the filtering is considered as successful and the section transfer starts. irq processing normal processing continues. the values of target_match and other_match are stored in the status word and the incomplete_filter bit is set along with the stream_number and filter_offset in the status word and pushed into the link_stat_fifo. the application software can use this information to complete the section filtering. af status bit lnk_stat_fifo.af maskable, no stream disabling. irq generation an lnk_af interrupt is generated if the af_irq bit is set for the current stream number and an af with at least one flag set is present in the packet and the previous one has been read by the st20. the first 8 bytes of the af are stored into the af[1..0]. if the af is less than 8 bytes, some payload bytes are written in the af buffer. if af length is 0, there is no match and no storage. irq processing normal processing continues. once the adaptation field information has been written into the af registers, the pcr counter value is latched and no new af information can overwrite it until the cpu has read the register af[1].if another af is received before the previous one has been read by the cpu, it is discarded.the af_flag is set in the status word along with the stream_number, and an interrupt is generated. sdav underflow status bit lnk_stat_fifo.su not maskable, no stream disabling. irq generation a sdav underflow is generated if a sdav packet has started to be output to the sdav port and no more data is present in the sdav block to be sent. irq processing the stream is not disabled. the output packet is corrupted and further data belonging to that packet is discarded. since the sdav operates independently from the rest of the link i/f, the stream_number present in the status word may not be relevant.when such a sdav underflow error occurs, the sdav_underflow bit is set along with the stream_number in the status word and the status word is written into the link_stat_fifo. interrupt source description table 67 interrupt sources
c o n f i d e n t i a l 14 link STI5518 128/294 7170179 d 14.5 dvd/link data analyzer the dvd data analyzer can only be used for the sector data structures described below. the dvd data analyzer facilitates trick modes and uses packet identification and video start-code detection functions. the dvd data analyzer is enabled by the start-code detector register bit lnk_mode.e_scd. the start-code detection circuits in the link are enabled when e_scd is set and dvdmode is selected bit (lnk_mode.dvd_m ) . packet identification and video start-code detection are two of the dvd data-analyzer functions. a byte counter tracks the start-code locations and is reset by the sector_start signal. the start-code type and location are written to the fram. the packet-type and the number of start-codes inside the sector are set by the lnk_stat_fifo register. processing a new sector when both the data_valid and sector_start signals go high, the first bit of a 2066 byte sector is transmitted over the serial interface from the front-end. each sector is treated independently of the adjacent sectors. any potential start- codes that are cross-sectored (straddled between two sectors) are flagged on the first sector. the st20 checks for a start-code at the beginning of the next appropriate sector when the start-code continuation flag has been set from the first sector. if lnk_mode.e_scd=0, all sectors are processed as in the STI5518. if lnk_mode.e_scd=1, all sectors are processed as in the STI5518, but the link hardware non-destructively evaluates the data as it passes through the link. sector data structure each sector consists of 2066 bytes transmitted over the serial interface in the following order: bytes 1:4 (4 bytes) for the sector id (identification information) (1 byte sector information, 3 bytes, byte 2 to 4, sector number); bytes 5:6 (2 bytes) for the iec (id error correction code); bytes 7:12 (6 bytes) of copyright management information (cpr_mai); sdav overflow status bit lnk_stat_fifo.so not maskable, no stream disabling. irq generation a sdav underflow is generated if the sdav buffer is full and new data is presented at the input of the buffer to be stored. irq processing the stream is not disabled. meanwhile, a new packet has possibly started being processed by the link i/f. note that the sdav block is supposed to accept data as delivered by the rest of the link i/f and can in no way suspend link i/f operation. when this occurs, the output of the current packet is aborted and all remaining data belonging to that packet is discarded. the read and write pointers are reset. if a new packet_start is already present, data input is not stopped and overwrites the discarded data. the read pointer points now to the first byte of this new packet. since the sdav operates independently from the rest of the link i/f, the stream_number present in the status word may not be relevant. when such a sdav overflow error occurs, the sdav_overflow bit is set along with the stream_number in the status word and the status word is written into the link_stat_fifo. interrupt source description table 67 interrupt sources
c o n f i d e n t i a l STI5518 14 link 7170179 d 129/294 bytes 13:2060 (2048 bytes) of the pack data referenced as d1:d2048; bytes 2061:2064 (4 bytes) for the edc (error detection code); bytes 2065:2066 (2 bytes) for the read solomon error codes sent by the channel ic. the sector number or sector id is saved for later processing. ? pack data ? is the area containing the packet identification and the mpeg data with the start codes. all other parts are passed without processing. identifying a packet 1 determine if bytes 13:16 (4 bytes) or d1:d4 contain the pack_start_code (0x000001ba) . if the pack-start code is found, continue. if the pack-start code is not found, write a ? 100 ? in register bit lnk_stat_fifo.pt. 2 determine the type of packet contained in the sector by parsing the packet header. 3 extract the first 4 bytes of the packet header, d15:d18, and set the packet-type bits of the link_stat_fifo regis- ter, according to the table below. 4 follow the actions identified for the packet-type. 4 bytes (1:4) 2 bytes (5:6) 6 bytes (7:12) 2048 bytes (13:1060) 4 bytes (2061:2064) 2 bytes (2065:2066) id iec cpr_mai pack data (d1:d2048) edc rsec table 68 sector data structure packet type start code action video packet 0x000001e0 set the flag identifying the packet as a video packet in the link_stat_fifo register and continue processing the data per the section on video packet processing. navigation packet 0x000001bb set the flag identifying the packet as a navigation packet in the link_stat_fifo reg- ister. no further action is required on this sector. audio packet or sub- picture packet (private_stream_1) 0x000001bd skip the next 4 bytes d19:d22 for the pes structure information. save the next byte, d23, and use its value in the next step. skip the number of bytes defined in d23. the next byte is the sub_stream_id byte. for example, if d23 = 2 then skip d24:d25. d26 would be the sub_stream_id byte. if d23 = 0 then d24 would be the sub_stream_id byte. if the sub_stream_id byte contains 10100xxxb , set the flag identifying the packet as a lpcm audio packet in the link_stat_fifo register. no further action is required on this sector. if the sub_stream_id byte contains 10000xxxb , set the flag identifying the packet as an ac3 audio packet in the link_stat_fifo register. no further action is required on this sector. if the sub_stream_id byte contains 001xxxxxb , set the flag identifying the packet as an subpicture packet in the link_stat_fifo register. no further action is required on this sector. if the sub_stream_id byte contains any other value, set the flag identifying the packet as unknown in the link_stat_fifo register. no further action is required on this sector. table 69 packet types and start codes
c o n f i d e n t i a l 14 link STI5518 130/294 7170179 d processing a video packet 1 find the beginning of the video mpeg bit stream payload within the sector and locate a video packet (0x000001e0). 2 skip bytes d19:d22 for the pes structure information. 3 save byte d23 for use in the next step. 4 skip the number of bytes defined in d23. the next byte is the first byte of the mpeg bit stream payload of this sec- tor. the byte range is from d24 to d44 (bytes 37-57 from start of sector). if d23 = 2, skip bytes d24 and d25, use byte d26 as the first mpeg byte. if d23 = 0, then d24 is the first mpeg byte. 5 provide a start-code detector for the incoming video bitstream. for start-codes located inside a sector (byte aligned) use the following table: for cross-sector start-codes, process the last 4 bytes (d2045:d2048) of the sector as follows: mpeg audio packet 0x000001cx set the flag identifying the packet as an mpeg audio packet in the link_stat_fifo register. no further action is required on this sector. mpeg-2 audio packet containing an exten- sion audio stream 0x000001dx set the flag identifying the packet as an mpeg audio packet in the link_stat_fifo register. no further action is required on this sector. unknown packet type any other code no further action is required on this sector. start code start code type 0x00000100 sc = ? 001 ? picture_start_code (32 bits) 0x000001b3 sc = ? 010 ? sequence_header_code (32 bits) 0x000001b4 sc = ? 011 ? sequence_error_code (32 bits) 0x000001b5 sc = ? 100 ? extension_start_code (32 bits) * report it only if the next four bits are one of the following: 0001 sequence extension id 0111 picture display extension id 1000 picture coding extension id * if not, do not report it in fram and continue to the next start code 0x000001b7 sc = ? 101 ? sequence_end_code (32 bits) 0x000001b8 sc = ? 110 ? group_start_code (32 bits) sc = ? 000 ? and sc = ? 111 ? not used table 70 identity for start-codes located inside a sector byte action d2045:d2048 0x000001b5 set flag (bit 7) in link_stat_fifo to indicate continuation of a sc into the next sector and write sc into fram using ? 001 ? as number of bytes carrying to the next sector. d2046:d2048 0x000001 set flag (bit 7) in link_stat_fifo register to indicate continuation of a sc into the next sector and write sc into fram using ? 010 ? as number of bytes carrying to the next sector. table 71 identity for cross-sector start-codes packet type start code action table 69 packet types and start codes
c o n f i d e n t i a l STI5518 14 link 7170179 d 131/294 reporting start codes the start-code information is reported in both fram and lnk_stat_fifo register. a portion of fram (from 0x00 to 0x7f) containing 128 32-bit words is used for reporting scs in this mode. the fram is partitioned into 4 sections of 32 words, each is used for one sector of sc information. the fram has data written to it only when the start-codes are found within the sector being processed, but the lnk_stat_fifo register is updated after every sector is transferred. fram address the fram address is defined as follows: four sections of the fram can be addressed using the two msbs of the 7-bit address. the two msbs are incremented in value for the next sector, only when the present sector has data to be written into the fram. if no data is written into the fram for the present sector, the two msbs remain the same for the present and the next sector. in this way, the st20 can keep track of data during jumps and skipping of non-video sectors. these two bits are reset by setting the start_code_enable signal to inactive, and then resetting it to active. the 5 lsbs of the fram address start at ? 00000 ? at each sector start. each time a start code is written into the fram, the 5 lsbs are incremented. a maximum of 31 words ( ? 11111 ? ) are written into the fram for any sector. all writing of data into the fram stops after ? 11111 ? for any sector, to prevent overwriting of earlier start codes found in this sector. therefore, the fram can report maximum of 31 start-codes in one sector. if a sector has more than 31 start-codes, the st20 must take action. the two msbs used to define the section of fram containing the start-code is communicated in bits 6:5 of the lnk_stat_fifo register. the number of start-codes found in the sector and reported in the fram, are communicated in bits 4:0 of the lnk_stat_fifo register. fram data start-code reports must contain the following information in a 32 bit word: for start-codes within a sector: for cross-sector start-code, one additional fram write is performed in the following format: d2047:d2048 0x0000 set flag (bit 7) in link_stat_fifo register to indicate continuation of a sc into the next sector and write sc into fram using ? 011 ? as number of bytes carrying to the next sector. d2048 0x00 set flag (bit 7) in link_stat_fifo register to indicate continuation of a sc into the next sector and write sc into fram using ? 100 ? as number of bytes carrying to the next sector. 31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 sector_id (15:0) start-code type location in the sector bitfield description 11:0 location of the last byte of the start-code in that sector. for the extension_start_code 0x000001b5, report the location of the next byte 14:12 start-code type 30:15 sector_id lsbs 31 indicates possibility of cross-sector start code case. if this bit is set, the software must check the beginning of the next continuous video sector to see if there is a start code 313029282826252423222120191817161514131211109876543210 1 sector_id (15:0) 14:12 00000000000 table 71 identity for cross-sector start-codes
c o n f i d e n t i a l 14 link STI5518 132/294 7170179 d if start-codes of more that 32 bits are found, the bits above bit 31 are not processed and the information is lost. 14.6 hard disk drive buffer control a hdd_bc (hdd buffer controller), positioned between the link interface and the st20 interconnect, traps the addresses associated with the video pid and adds an offset in order to establish a much bigger buffer within the external memory. in normal operation, the base address of the circular buffer in external memory is set by dma_low_address programmed in lnk_stream_conf3, and dma_high_address and dma_bank_address programmed in lnk_stream_conf2 register. the circular buffer size can be programmed to a maximum of 8k by lnk_streamconf2. in hdd mode, the buffer size is programmable but its position in the external memory must be on a boundary that is an integer multiple of its size. to use the hdd_bc, the link circular buffer must be set to its maximum 8kbyte size. in hdd mode the base address of the circular buffer is set in exactly the same way as in normal mode until the buffer reaches 8k, then the dma_high_address is incremented by the hdd_bc and programmed in the hdd register lnk_hdd_addrhigh. the size of the circular buffer is now controlled by the hdd_bc through register lnk_hdd_bufsize, and the stop mechanism in the link interface must be disabled by programming the stop pointer location outside the 8k circular buffer (by register lnk_stream_conf_2 bits stop_addr). this causes an hdd link interrupt (interrupt assignment number n=29). all of the hdd dedicated registers are described in the hdd buffer control section in the link chapter of the STI5518 register manual. bitfield description 11:0 00000000000 14:12 number of bytes carrying to the next sector of a possible start code (max value is ? 100 ? ). 30:15 sector_id lsbs 31 indicates possibility of cross-sector start code case. if this bit is set, the software must check the beginning of the next continuous video sector to see if there is a start-code
c o n f i d e n t i a l STI5518 15 mpeg video decoder 7170179 d 133/294 15 mpeg video decoder the mpeg video decoder decompresses a mpeg 2 bit-stream and constructs a picture. the display functions are described in sub-picture decoder on page 150 and the mpeg video decoder registers are described in the STI5518 register manual . 15.1 decoder operation the video decoder is a picture decoder; it decodes one picture and then stops until instructed to decode the next picture in the video bit-stream. normally, the decoding of a new picture starts in response to the start-of-display of a new picture. the registers whose contents can change from picture to picture are double-banked and are updated automatically when decoding starts. the bit-stream is read from the bit-buffer into the variable-length code decoder (vld), and picture can be built. any required predictors are fetched from the appropriate area of the external memory, and the reconstructed picture is written back into the area of this memory assigned to the decoded picture. while a picture is being decoded, the start-code detector locates the start of the next picture header. the cpu then uses this to set-up the double-banked registers to decode the next picture. all of these tasks can be synchronized using interrupts generated on start-code hits and vertical-sync signals. start code search the video decoder is able to decode in its entirety a video bit-stream from the slice layer downwards. the higher layers (i.e. picture and upwards) are decoded by the driver in order to extract the information needed for decoding and set up the appropriate video decoder registers and quantization tables. since the header information is byte-aligned and requires minimal interpretation, this task represents only a small load on the cpu. the start code detector parses the bit-stream stored in the bit buffer and locates start codes corresponding to picture layer and above. when one of these start codes has been found, the start code detector stops and raises an interrupt. the cpu is then able to read the header data following the start code. the start code detector starts automatically whenever the decoding of a new picture starts and on user command. in normal operation, start code parsing is performed one picture in advance of decoding. bandwidth reduction mode bandwidth reduction mode is the only decoding mode that is supported by the device. in this mode, where i, p and b- frames are decoded into and displayed from frame buffers in external memory, the decoder uses three frame buffers in external memory. this mode opimizes memory bandwidth use. 15.2 reset hard reset is a global signal and is described in the system services chapter. the following types of soft reset can be used for the video decoder: total soft reset is generated by setting and resetting bit vid_ctl.srs and register aud_res. they must be set for a duration of at least 1s. audio, video and sub-picture subsystems may be individually soft reset by setting and resetting vid_sra and aud_res, vid_srv and spd_spr respectively. pipeline reset is generated by setting and resetting bit vid_ctl.prs. it must be set for a duration of at least 40ns. after a soft reset, all processes concerning decoding and bit buffer control are reset. any data remaining in the bit buffer, the compressed data fifo and the start code detector fifo are lost.
c o n f i d e n t i a l 15 mpeg video decoder STI5518 134/294 7170179 d the interrupt unit is reset. all registers maintain their contents and the display process is not disturbed. a soft reset would normally be used when the decoding of the current bit-stream must be terminated and it is required to restart on a new sequence. after a hard or a soft reset or a video soft reset, the first task performed by the pipeline when it has been enabled will always be a search for the beginning of a new sequence. the bit buffer data is flushed until the first picture start code following a sequence start code is detected by the pipeline, at which time it stops. at this point normal picture decoding behavior is resumed. after a hard or a soft reset, the first search performed by the start code detector in response to the first dsync will always be a search for a sequence start code, after which it stops. after this, the start code detector operates normally. a pipeline reset terminates the decoding of the current picture. the remaining bits of the picture are flushed from the bit buffer until the next picture start code is detected by the pipeline. at this point normal behavior is resumed, i.e. the pipeline waits for the next picture decoding instruction. no other part of the circuit is affected by a pipeline reset. a pipeline reset would normally be used as part of a manual error recovery procedure. a pipeline reset has no effect if the decoding pipeline is in its idle state. 15.3 bit buffer and start-code detection (video) 15.3.1 bit buffer the transfer of compressed data is carried out using the link dma engines. compressed data can be taken from any memory space visible to the cpu and transferred to the relevant elementary stream decoder. 15.3.2 start code detection the start code detector operates in parallel with the decoding pipeline. the purpose of this unit is to allow external access to the header data which follows start codes in the input bit-stream. compressed data is read twice from the bit buffer- once into the pipeline, and once into the start code detector through the 128-byte header fifo. the transfer of data into the header fifo does not affect the bit buffer level; only the data transfer into the pipeline can reduce the bit buffer level. start code detection is initiated in two ways: automatically whenever the internal event dsync occurs. dsync is derived from vsync as described in decoding task on page 144 . a dsync is generated every time the pipeline starts a new picture decoding task. by software writing to the vid_hds register with bit vid_hds.hds set. when start code detection has been started, data is read continuously from the bit buffer into the header fifo and parsed by the start code detector, which receives the fifo output data. when a start code is detected, the data scanning stops and the status bit vid_sta.sch becomes 1. when a start code has been detected, it can be identified by reading the vid_hdf register. the start code detector detects all start codes other than the codes from 0x00000102 through to 0x000001af. the first slice start code 0x00000101 can be optionally detected to help driver development.
c o n f i d e n t i a l STI5518 15 mpeg video decoder 7170179 d 135/294 the register vid_hdf should always be read twice to return a 16-bit value. the most significant byte is read first. after detection of a start code, vid_hdf will return one of the 16-bit values shown below: the first step is to examine the first byte read from vid_hdf. if this contains 0x01, then the start code can be identified by a second read at the same address. if the first byte is not 0x01 then it must be the last byte of the start code and the second byte is the first byte of the header data. in both cases subsequent reads from vid_hdf will give access to the header data which follows the start code. scanning for start codes will recommence on the next dsync or a write to vid_hds.hds. whenever a start code has been detected, the vid_hdf register must be read in order for the start code detector to restart correctly . the number of reads before a manual or automatic (dsync) restart must always be even. the first start code search after a hard or soft reset will be a search for a sequence header start code; all other start codes will be ignored. when this start code has been read, all subsequent searches will look for any start codes other than slice start codes. the two status bits vid_sta.hfe (header fifo empty) and vid_sta.hff (header fifo full) indicate the state of the header fifo. reading from hdf must never be performed if vid_sta.hfe is 1. vid_sta.hff is set whenever the header fifo contains at least 66 bytes. the start code detector can also be programmed to stop on the first slice of the picture. this allows the use of the start code search even after reception of the picture start code. all header data that is not used by the application can then be skipped without risk, in order to jump to the next picture start code. this mode is enabled by setting bit vid_hds.sos. to differentiate between first slice start code (00 00 01 01) and other start codes, it is possible to detect at which position (msb or lsb) the last byte of start code is positioned in the vid_hdf register. register bit vid_hds.scm when set indicates that the last byte of start code is held by the msb of vid_hdf; it is zero otherwise. 15.3.3 handling time-stamps the video decoder accept mpeg-1 system streams and mpeg-2 packet streams. for video/audio elementary streams, time-stamps contained in the video packet headers are associated with the picture decode time. this is important because the number of pictures which may be stored in the bit-buffer at any instant is unknown, and therefore there is a variable delay between the input of a picture into the bit buffer and its entry into the decoding pipeline. there is a 24-bit counter at the input and at the output of the cd fifo - bit buffer - header fifo chain, as shown in figure 75 . each time a byte is written into the cd fifo the counter ? cdcount ? is incremented. each time a 16-bit word figure 74 states of vid_hdf after detection of a start code vid_hdf last byte of start code first header byte vid_hdf 01 last byte of start code first read second read header data first header byte first header byte third read
c o n f i d e n t i a l 15 mpeg video decoder STI5518 136/294 7170179 d is read from the header fifo, the counter ? scdcount ? is incremented. both of the counters are reset by a hard or soft reset. both are modulo 2 24 , that is, the state following ffffff is 000000. when the first byte of video data from a new packet containing a time-stamp is written into the cd fifo, vid_cdcount[23:0] is read. this value and the time-stamp is recorded in a fifo. when a picture start code is detected by the start code detector, vid_scdcount is read. if this value multiplied by two, is greater (modulo 224) than the last cdcount in the fifo, then the next picture to be decoded is associated with the time-stamp stored at this position of the fifo. the ? time-stamp association ? information is available in the pes_tsx register. the same mechanism is implemented for the ? dsm trick mode ? association (register pes_tmx). 15.4 video decoding pipeline control note the video decoder only operates in bandwidth reduction mode. the pipeline is the core of the decoder. it is that part of the circuit which converts the compressed bit-stream data for each picture into a decoded (or reconstructed) picture. these pictures can be frame or field pictures. the operation of the pipeline is controlled picture-by-picture. the decoding of a new picture can potentially start on every vsync, but usually the rate of decoding is faster than the vsync rate. the pipeline is controlled by the pipeline controller. when the pipeline controller starts the decoding pipeline a dsync signal is issued and vid_sta.psd is set. this signal is also sent to the start code detector. when the pipeline has completed its decoding operation, a completion signal is sent to the pipeline controller, which is then able to launch another decoding operation, either immediately or when the next vsync occurs. the pipeline controller interprets certain bits of the decoding instruction, which must be set up by the user before the start of each new task. the remaining bits of the instruction define the decoding task itself. the pipeline receives its compressed data from the bit buffer. this data is first processed by the variable length decoder (vld) which regenerates the run/level coded dct coefficients and the motion vectors (if present) for each macroblock. the picture data is reconstructed by passing the run/level data through the inverse quantizer and inverse dct blocks. this is then added to the predictors which have been fetched from the memory taking into account the macroblock prediction modes and motion vectors. figure 75 handling time-stamps with vid_cdcount and vid_sdcount sdram video bit-buffer v l d s c d video decoder vid_sdcount[23:0] sdram arbiter (lmc) st20 arbiter and bus vid_cdcount[23:0] ... audio cd fifo sub-picture cd fifo pes parser video cd fifo (128 bytes)
c o n f i d e n t i a l STI5518 15 mpeg video decoder 7170179 d 137/294 finally, the decoded picture is written back into the memory, from where it can be accessed by the display unit for output. the pipeline is also able to skip through picture data for various reasons. the different possibilities are: skip to next sequence. this occurs unconditionally on the first instruction execution after a hard or soft reset (see reset on page 133 ). compressed data is skipped until the first picture start code following a sequence start code is found. the pipeline then indicates task completion and waits for a new instruction. skip to next picture. this occurs either after a pipeline reset (see reset on page 133 ) or when the decoding instruction specifies that one or two pictures should be skipped (see decoding task on page 144 ). in the first case compressed data is skipped until the next picture start code is found, after which the pipeline indicates task completion and waits for a new instruction. in the second case, after the skipping operation the decoding of the following picture is started immediately. skip to next slice. this occurs after automatic error concealment (see error recovery and missing macroblock concealment on page 145 ). compressed data is skipped until the next slice start code in the picture is found, after which normal decoding resumes. before starting to decode a sequence, certain static parameters must be set up. these are: mpeg-1 or mpeg-2 mode selection. bit vid_ppr2.mp2 must be set for an mpeg-2 sequence, reset for an mpeg-1 sequence. decoded picture size. register vid_dfw must be set up with the picture width in macroblocks, and register vid_dfs must be set up with the number of macroblocks in the picture. decoding is enabled by setting bit vid_ctl.edc. 15.5 quantization table loading the two quantization matrices (intra and non-intra) used by the inverse quantizer must be initialized by the user. there are no built-in quantization matrices. therefore, they must be loaded either with default matrices or with those extracted from the bit-stream by the st20. the quantization tables are double-buffered. this enables one or both tables to be updated without disturbing the decoding task in progress. the video decoder maintains two bits which record whether one or both of the tables have been modified. a modified table is automatically brought into operation at the start of the next decoding operation, i.e. when the next dsync occurs. after a hard reset, the same pair of tables is always selected. the data previously loaded into the tables is not affected. other types of reset have no effect on the quantization tables. the quantization tables are written at the address held in the register vid_qmw. bit vid_hds.qmi is used to select the intra or non-intra quantization table; when it is set, the intra table is selected; when clear the non intra table is selected. 15.6 memory mapping of data two types of external sdram can be mapped from the STI5518. 1 or 2 x 16-mbit sdram 1 x 64-mbit sdram this section discusses video decoder memory (sdram) addressing, 32-bit word addressing for the cpu and 64-bit word addressing for fifo for both of these types of external sdram.
c o n f i d e n t i a l 15 mpeg video decoder STI5518 138/294 7170179 d 15.6.1 mapping 1 or 2 x 16-mbit sdram video decoder memory sdram addressing (for 1 or 2 x 16-mbit sdram) the locations in an sdram are addressed row-by-row, bank a then bank b, as shown below: 32-bit word addressing for the cpu (for 1 or 2 x 16-mbit sdram) the cpu accesses the sdram by using a 19-bit address for each 32-bit word. it is the task of the sdram memory controller to re-map the logical address space of the cpu onto the sdram address space. the logical address map seen by the cpu is different from the one described above. for each row, both banks are used. the addresses seen by the cpu through the sdram interface are counted in the following order: bank a row0 --> bank b row0 --> bank a row1 --> bank b row1 --> ... and so on, as illustrated in figure 77 : when using a second sdram chip, addresses continue in a similar way, starting from the next address above the first sdram, as illustrated in figure 77 on page 138 . a maximum of two sdram chips is supported. figure 76 standard addressing in a sdram (16-bit words) for 1 or 2 x 16-mbit sdram figure 77 32-bit word addressing, as seen by the cpu for 1 or 2 x 16-mbit sdram row 0x080000 0x0fffff row 0x0000ff 0x07ffff 0 bank a bank b 0x080000 row n 0x0fffff 0x07ffff row n 0x0000ff row n 0x00007f 0 row n 0x0800ff 0x000080 0x0001ff 0x0002ff sdram 0 sdram 1 the system supports up to 2 sdram chips bank a bank b bank a bank b
c o n f i d e n t i a l STI5518 15 mpeg video decoder 7170179 d 139/294 64-bit word addressing for fifo processes (for 1 or 2 x 16-mbit sdram) the video decoder uses circular buffers mapped into external sdram which act as software fifos. the processes pertaining to these circular buffers are managed with a 64-bit granularity. the memory mapping for these buffers is similar to that of the cpu and is shown in figure 81 on page 141 . when using a second sdram chip, addresses continue in a similar way, starting from the next address above the first sdram. a maximum of two sdram chips is supported. figure 78 64-bit word addressing for fifo processes for 1 or 2 x 16-mbit sdram 0x040000 row n 0x07ffff 0x03ffff row n row n 0x00003f 0 row n 0x04007f 0x000040 0x0000ff sdram 0 sdram 1 0x00007f 0x000080 bank a bank a bank b bank b
c o n f i d e n t i a l 15 mpeg video decoder STI5518 140/294 7170179 d 15.6.2 mapping 1 x 64-mbit sdram video decoder memory sdram addressing (for 1 x 64-mbit sdram) the locations in an sdram are addressed row-by-row, bank a, b , c then bank d, as shown below: 32-bit word addressing for the cpu (for 1 x 64-mbit sdram) the cpu accesses the sdram by using a 21-bit address for each 32-bit word. it is the task of the sdram memory controller to re-map the logical address space of the cpu onto the sdram address space. the logical address map seen by the cpu is different from the one described above. for each row, both banks are used. the addresses seen by the cpu through the sdram interface are counted in the following order: figure 79 standard addressing in a sdram (16-bit words) for 1 x 64-mbit sdram bank d row bank c bank b row bank a 0x0fffff 0x000000 0x1fffff 0x100000 0x200000 0x300000 0x2fffff 0x3fffff
c o n f i d e n t i a l STI5518 15 mpeg video decoder 7170179 d 141/294 bank a row0 --> bank b row0 --> bank a row1 --> bank b row1 --> ... --> bank a row 4005 --> bank b row 4005, --> bank c row 0 --> bank d row 0... and so on, as illustrated in figure 80 on page 141 : 64-bit word addressing for fifo processes (for 1 x 64-mbit sdram) the video decoder uses circular buffers mapped into external sdram which act as software fifos. the processes pertaining to these circular buffers are managed with a 64-bit granularity. the memory mapping for these buffers is similar to that of the cpu and is shown in the figure below. figure 80 32-bit word addressing, as seen by the cpu for 1 x 64-mbit sdram figure 81 64-bit word addressing for fifo processes for 1 x 64-mbit sdram 0x100000 row n 0x1fffff 0x0fffff row n 0x0000ff row n 0x00007f 0 row n 0x1000ff 0x000080 0x0001ff 0x0002ff bank d bank a bank c bank b 0x080000 row n 0x0fffff 0x07ffff row n row n 0x00003f 0 row n 0x08007f 0x000040 0x0000ff 0x00007f 0x000080 bank a bank c bank d bank b
c o n f i d e n t i a l 15 mpeg video decoder STI5518 142/294 7170179 d 15.6.3 memory segments the circular-buffer start and end pointers are programmed by the user, in segments, where each segment is 256 bytes. the values in the configuration registers are numbers of segments. for example a value of 4 means 4 x 256 bytes = 1kbyte or 128 x 64-bit words. this would result in a pointer pointing to a 64-bit word address of 128 (0x80). this address would be physically mapped to the first word in the second row of bank a of sdram 0, as shown below; 15.6.4 arrangement of pixel-pairs inside a luma sdram row every sdram row in a luma frame contains 256 16-bit words and can store up to two luma macroblocks. every 16-bit word contains a pair of horizontally adjacent luma pixels. the row itself stores a pair of horizontally adjacent luma macroblocks. the pixel pairs are arranged in line order; the first 16 words store the first line of pixels for the two macroblocks, the next 16 words the second line and so on, as shown below: figure 82 sdram segments as seen by the user figure 83 arrangement of pixel pairs in a luma sdram row 32 76 10 54 8 address = 0x80 bank b bank a 16-bit word addresses in sdram row 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f arrangement of luma pixel pairs y = y y y y y y y y y y y y y y y 16-bit word addresses in sdram row f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff arrangement of luma pixel pairs y y y y y y y y y y y y y y y y macroblock 0 macroblock 1 2 pixels
c o n f i d e n t i a l STI5518 15 mpeg video decoder 7170179 d 143/294 15.6.5 arrangement of pixel-pairs inside a chroma sdram row every sdram row in a chroma frame contains 256 16-bit words and can store up to four chroma macroblocks. every 16-bit word contains a pair of horizontally adjacent 8-bit chroma pixels. the row stores pixel pairs in line order for macroblocks 0 and 1 and then macroblocks 2 and 3. the cb and cr words are interleaved two by two in the linear addressing order, as shown below: 15.7 using picture pointers before decoding a picture, the following frame buffer pointers must be set up: vid_rfc, vid_rfp for reconstructed frame pointers for chroma and luma. these pointers define the memory buffer to which the decoded picture is written. vid_ffc, vid_ffp for forward prediction frame pointers for chroma and luma. these pointers define the areas in memory from which the predictors are fetched. vid_bfc, vid_bfp for backward prediction frame pointers for chroma and luma. these pointers define the areas in memory from which the predictors are fetched. the displayed frame pointers, vid_dfc, vid_dfp, are described in sub-picture display on page 153 . the following rules must be followed when using prediction-frame pointers: 1 pictures are always stored as frames of interleaved lines. therefore, to access a field (top or bottom), the starting address of the frame must be defined. 2 p-frame picture (frame, field or dual-prime prediction): vid_ffp and vid_ffc are set to the address of the predic- tor frame (in which the two predictor fields lie). vid_bfp and vid_bfc are not used. 3 b-frame picture (frame or field prediction): vid_ffp and vid_ffc are set to the address of the forward predictor frame (in which the two predictor fields lie). vid_bfp and vid_bfc are set to the address of the backward predic- tor frame (in which the two predictor fields lie). figure 84 arrangement of pixel pairs in a chroma sdram row 16-bit word addresses in sdram row 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f arrangement of luma pixel pairs cb = cb cr cr cb cb cr cr cb cb cr cr cb cb cr cr 16-bit word addresses in sdram row 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f arrangement of luma pixel pairs cb cb cr cr cb cb cr cr cb cb cr cr cb cb cr cr macroblock 0 macroblock 1 2 pixels 16-bit word addresses in sdram row 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f arrangement of luma pixel pairs cb cb cr cr cb cb cr cr cb cb cr cr cb cb cr cr 16-bit word addresses in sdram row f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff arrangement of luma pixel pairs cb cb cr cr cb cb cr cr cb cb cr cr cb cb cr cr macroblock 2 macroblock 3
c o n f i d e n t i a l 15 mpeg video decoder STI5518 144/294 7170179 d 4 p-field picture (field, 16 x 8 or dual-prime prediction): when decoding either field, vid_ffp and vid_ffc are set to the address of the previous decoded i or p frame. vid_bfp and vid_bfc are not used. 5 b-field picture (field or 16 x 8 prediction): vid_ffp and vid_ffc are set to the address of the frame in which the two forward predictor fields lie. vid_bfp and vid_bfc are set to the address of the frame in which the two back- ward predictor fields lie. 6 i-pictures: for i-picture decoding, no predictors are necessary, but vid_ffp and vid_ffc must be set to the address of the last decoded i- or p-picture for use by the automatic error concealment function. 15.8 video pipeline 15.8.1 decoding task a task is a single picture decoding operation. a task is specified by the task description or instruction, which is set up before the decoding of each picture. a task starts when the internal signal dsync is generated. a task completes (the decoder becomes idle) when the picture is entirely reconstructed in the memory and the picture header of the following picture is detected by the pipeline. the instruction is double buffered, so that during execution of a decoding task, the instruction for the next task can be set up by the cpu. when the next instruction is activated, a dsync can be generated and the next decoding task started. the buffering mechanism is illustrated in the figure below. note that some instruction bits are latched by vsync, others by a signal from the pipeline controller ? new instruction ? . the instruction is written into registers vid_ppr1 and vid_ppr2. if a new instruction is not written, the task descriptor will be the same as the previous one. normally, it is vsync starts the execution of a new instruction and, thus, the generation of dsync. if however, a vsync occurs before task completion (i.e. before the pipeline becomes idle), the start of the next task is delayed until the present one is completed. in this way, the picture decoding can extend beyond the nominal period by one or two vsync periods. three status bits (and thus interrupts) are associated with pipeline control: vid_sta.psd indicates the occurrence of a dsync. vid_sta.pii indicates that the pipeline is idle. vid_sta.dei indicates that the decoder is idle, i.e. the pipeline is idle and the next picture start code has been found. figure 85 instruction buffering ? new instruction ? or vsync from cpu ta sk description instruction register slave register registers vid_ppr1, vid_ppr2, vid_tis.skp[1:0]
c o n f i d e n t i a l STI5518 15 mpeg video decoder 7170179 d 145/294 the operation of the pipeline controller is shown in the diagram below. the abbreviations used in the diagram are explained in the following table. the instruction bits which affect state transitions are vid_tis.exe and vid_tis.fis. the events to which the controller responds are: vsync, which could be a vsync top or a vsync bottom and idle representing the idle state of the pipeline. 15.8.2 error recovery and missing macroblock concealment for the video decoder, there are four levels of error-detection and recovery: bit-stream syntax error detection with the option of automatic missing macroblock concealment; bit-stream semantic error detection with the option of automatic concealment or skip to the next picture; figure 86 task control state diagram abbreviation meaning erc automatic error concealment exe.fis both vid_tis.exe and vid_tis.fis are set exe.vsync bit vid_tis.exe set when external vsync occurs pii pipeline idle dei decoder idle interrupt generated psc picture start code psd pipeline start decode interrupt generated seq sequence start code skip and decode vid_tis = exe | skp[01] and vsync occurred skip and stop vid_tis = exe | skp[11] and vsync occurred skip twice and decode vid_tis = exe | skp[10] and vsync occurred table 72 state transition abbreviations reset state seeking seq idle skipping skipping twice skipping once waiting for data decoding picture error concealment (then stop) reset exe.vsync or exe.fis psd found first psc after seq dei or exe.vsync exe.fis psd bit buffer empty new data input end of erc syntax error found next psc skip once and decode end of decode and psc found pii dei psd found next psc psd skip twice and decode skip and stop found next psc
c o n f i d e n t i a l 15 mpeg video decoder STI5518 146/294 7170179 d pipeline overflow or underflow error detection; user-initiated skip to next sequence using soft reset. syntax error detection and concealment in normal operation of the STI5518, error concealment must always be enabled, i.e. vid_ctl.edc should be reset. if the vld detects a syntax error in the bit-stream, the pipeline will copy macroblocks from the previous picture using the motion vectors reconstructed for the previous row of macroblocks in the current picture, while scanning the bit- stream until a slice start code is detected. at this point normal decoding resumes. if the slice in which the error occurred was the last one in the picture, concealment will continue until the end of the picture, at which time the pipeline stops normally (assuming that the following picture start code is intact). the concealment macroblocks are accessed using the pointers vid_ffp and vid_bfp. lost macroblocks in the first row are copied directly from the previous pictures (i.e. as p-macroblocks with zero motion vectors). if an intra picture is coded with concealment motion vectors, these will be used. if not, then the concealment will be a simple copy from the previous picture using zero vectors. even in intra pictures, the pointer vid_ffp must be set up. the table below gives the rules that are used for fetching concealment macroblocks. if an error is detected in the bit-stream before it enters the parser, then an error start code can be inserted into the bit- stream in order to initiate concealment. however, when doing this there are certain restrictions on the placement of the error start code in order to avoid emulation of other start codes. an application note is available on this topic. overflow or underflow error an overflow error occurs whenever the pipeline reconstructs more macroblocks than are defined by the decoded picture size, vid_dfs. this can occur when the input data to the decoder contains undetected errors. this condition is signalled by bit vid_sta.ser. decoding is automatically halted when this error is detected. in order to restart decoding a pipeline reset must be performed. an underflow error occurs whenever the pipeline reconstructs less macroblocks than are defined by the decoded picture size, vid_dfs. this condition is signalled by bit vid_sta.pde. decoding is automatically halted when this error occurs. in order to restart decoding a pipeline reset must be performed. picture type macroblock type fetch rule i-picture i-macroblock without vectors copy with zero motion. i-macroblock with vectors copy as forward predicted macroblock. p-picture i-macroblock without vectors copy with zero motion. i-macroblock with vectors copy as forward predicted macroblock. p-macroblock copy using stored vector. p-field-macroblock copy in field mode using both vectors. skipped macroblock copy with zero vector. dual-prime macroblock copy using stored vector. b-picture i-macroblock without vectors copy with zero motion. i-macroblock with vectors copy as forward predicted macroblock. forward macroblock copy using stored vector. backward macroblock copy using stored backward vector. bidirectional macroblock only the forward vectors are stored, concealed as forward macrob- lock. skipped macroblock copy in frame mode using the same mode and vectors as the previ- ous macroblock. table 73 rules for fetching concealment macroblocks
c o n f i d e n t i a l STI5518 15 mpeg video decoder 7170179 d 147/294 15.9 pes parser description the pes parser is situated between the st20 arbiter/bus and the compressed data fifos of the video/audio core. it has a 100 mbits/sec (max burst) bit rate, and allows the following input streams: packetized pes (mpeg-2), iso 13818-1 mpeg-1 system layer (iso 11172-1) the mpeg2 pes &mpeg1 system parser accepts pes streams in the same way that pure audio or vi deo streams are accepted. for packetized elementary stream data which is demultiplexed from a transport stream (mpeg-2), the data stream consists of concatenated, incomplete packets of audio, and video pes. to handle this configuration, the STI5518 contains two separate parsers: one for the audio (audio pes parser in audio decoder) and one for the video (mpeg2 pes & mpeg1 system parser). as the audio or video data is input, it is demultiplexed by each parser and the audio / video streams are placed in their respective buffers. for program stream data or mpeg-1 systems stream data, the audio and video packets are complete so that a single parser (mpeg2 pes & mpeg1 system parser) can be used. the packets are internally separated into video and audio streams. if required, the two parsers can still be used but the packets must be separated by the st20 (recommended mode). see the figure below. when the mpeg2 pes & mpeg1 system parser is configured to accept mpeg-2 pes audio/vi deo packets (mode 3), the parser extracts audio & video bit-streams in accordance with the programmed stream id. for the audio stream this is contained in pes_cf1; for the video stream in pes_cf2. any audio or video packets which are not selected for figure 87 system parser internal architecture st20 arbiter and bus mpeg2 pes parser & mpeg1 system parser video cd fifo (128 bytes) video bit buffer (sdram) video decoder pts/dts fifo audio cd fifo (128 bytes) audio bit buffer (sdram) audio pes parser audio decoder sub-picture cd fifo (128 bytes) sub-picture bit buffer (sdram) sub-picture decoder video elementary stream audio pes packet or audio elementary stream sub-picture elementary stream *1 *2 1* this path can be used for audio mpeg1 system stream decode or audio mpeg2 program stream decode. however, this path is more sensitive to errors retrievals. the mpeg2 pes & mpeg1 system parser can not output elementary stream on this path. 2* the audio pes parser is handled by the audio decoder (software parser).
c o n f i d e n t i a l 15 mpeg video decoder STI5518 148/294 7170179 d decode (because their stream ids do not match the programmed values) are discarded. the audio pes are output on path 1 (see figure 87 on page 147 ). when used for decoding program streams or mpeg-1 system streams, the audio, video and system level data are automatically separated internally to the mpeg2 pes & mpeg1 system parser. time-stamp association is su pported by the decoder. during parsing, decode or display time-stamps (dtss or ptss, selected by pes_cf1.sdt) are stored in an internal fifo. when the image corresponding to these time-stamps is decoded (or, in the case of video, about to be decoded) the corresponding time-stamp is made available and a flag or interrupt is given. functional modes the parsers are enabled by setting register pes_cf2.ss for the video parser, and registers streamsel/ decodesel for the audio parser. depending on the required mode, one or both of the parsers are required. four different modes can be configured with the two mode bits of register pes_cf2[7:6]: mode 0: automatic configuration. the parser examines the incoming stream and self-configures for decode. the mode selected can be read back from pes_tm2[1]. mode 1: mpeg-1 system stream decode. single data strobe input format. the audio elementary stream is extracted by the mpeg-2 pes parser & mpeg-1 system parser block and sent to the cd audio fifo. mode 2: mpeg-2 pes decode. twin data strobe input format. the video pes stream and the audio pes stream are sent separately and respectively to mpeg-2 pes parser & mpeg-1 system parser block and audio cd fifo. this is the most common way to enter data into the circuit. mode 3: mpeg-2 whole pes audio/video packets. single data str obe input format. this is used to decode mpeg- 2 program streams. the audio pes are output on path 1 (see figure 87 on page 147 ) extracted by the mpeg-2 pes parser & mpeg-1 system parser block and send to the cd audio fifo. the video parser is reset by setting pes_cf2.ss to 0. 15.10 enhanced trick-modes dvd trick-modes, especially backward-mode, require more video decoding flexibility than standard mpeg applications. the STI5518 supports the following trick-mode features: programmable video cd (compressed data) fifo pointer programmable scd (start code detector) pointer programmable vld (variable length decoder) pointer
c o n f i d e n t i a l STI5518 15 mpeg video decoder 7170179 d 149/294 the figure below illustrates the video decoder features which enhance dvd trick-modes. programming a video cd fifo pointer the video cd fifo destination is programmed inside the sdram shared memory (up to 64 mbits). 1 set register bit vid_tp_ldp.tm to ? 1 ? . 2 flush the fifo by writing 64 bytes (0xff) to the cd fifo. 3 write a new 20-bit cd pointer value to the vid_tp_cd register (this is a 3 x 8-bit register). 4 set bit cwl of register vid_cwl to ? 1 ? . this starts the fifo reset mechanism. status bit cwr of the vid_its register indicates that the cd fifo is ready for transfer into sdram. register vid_tp_calinit can be used for overwrite protection. programming an scd pointer 1 set register bit vid_tp_ldp.tm to ? 1 ? . 2 write a new 20-bit scd pointer value to the vid_tp_scd register (this is a 3 x 8-bit register). 3 set bit stl of register vid_stl to ? 1 ? . this starts the fifo reset mechanism. status bit swr of the vid_its register indicates that the scd fifo is ready for transfer into sdram. programming a vld pointer 1 set register bit vid_tp_ldp.tm to ? 1 ? . 2 set register vid_trf with the temporal reference, and set register vid_tp_vld with a new read-pointer. 3 set bit tr_tml of register vid_trf to ? 1 ? . status bit tr_ok of register vid_its indicates that the vlr read pointer has been loaded into the memory controller, and that the vld is ready to decode the selected picture. figure 88 enhanced trick-mode support sdram video bit-buffer v l d s c d video decoder sdram arbiter (lmc) st20 arbiter and bus ... audio cd fifo sub-picture cd fifo pes parser video cd fifo (128 bytes) these three pointers are programmable
c o n f i d e n t i a l 16 sub-picture decoder STI5518 150/294 7170179 d 16 sub-picture decoder 16.1 introduction a hardware sub-picture decoder is integrated in the STI5518. the sub-picture bit-buffer that contains sub-picture units (spu) is integrated in sdram external memory and has a programmable size. its position and size can be set in multiples of 2 kbytes. the sub-picture bit buffer is set-up at power-up reset. during player operation, its size and location are constant. compressed data is input into the bit-buffer using a dma, or by a cpu write. once control is given to the sub-picture decoder, it runs autonomously until stopped by software control. the sub-picture decoder can decode complete sub- picture units - which consist of a sub-picture unit header, compressed pixel data and the display control sequence table - without any interaction from the cpu. the sub-picture decoder can also be used as a hardware cursor unit. the priority of the sub-picture is first raised by programming a register so it is in front of all the other display planes. a cursor can be defined using an optionally compressed (run-length encoded) bitmap stored in external sdram. the bitmap can be any size up to a full screen. per-pixel alpha-blending factors can be defined for each cursor to provide anti-aliasing with the background. the cursor is then moved around using register writes into x and y coordinate registers. the figure below illustrates the sub-picture decoder architecture. figure 89 display planes figure 90 sub-picture unit architecture sub-picture optional positions decompressed video sub-picture plane on-screen display sub-picture plane dcsq parser sub-picture bit buffer highlight area detect sub-picture area detect 8 x pci area detect run length decoder area prioritization logic 8 x line control luts color and contrast mux mixing unit sub-picture lut highlight lut main lut
c o n f i d e n t i a l STI5518 16 sub-picture decoder 7170179 d 151/294 16.2 buffer management and pointers there are four registers which control the sub-picture bit buffer read and write processes, as shown in figure 91 : bit buffer base address (vid_spb). this is an offset relative to the st20 sdram base address. it is programmed in units of 2 kbytes. bit buffer end address (vid_ spe). this address is an offset relative to the st20 sdram base address. it is programmed in units of 2 kbytes. bit buffer read pointer (vid_spread). it is set by software for each sub-picture unit. this is done before control is given to the sub-picture hardware decoder. this register is double buffered. the shadow register is updated with each field vsync event. this pointer is an offset relative to the st20 sdram base address. it is programmed in units of 64-bit words. bit buffer write pointer (vid_spwrite). it is set by the st20 before transferring each sub-picture unit into the bit buffer. this pointer is an offset relative to the st20 sdram base address. it is programmed in units of 64 bit words. 16.3 operation each sub-picture unit data-buffer start-position is programmed using the register vid_spwrite. subsequently the sub- picture header, the pixel data, the display control sequences are sent via fifos to the sub-picture decoder. write into fifos is done by dma or by cpu write. only data belonging to the sub-picture unit (spuh, pxd, dcsqt) are transferred into the sub-picture bit buffer. sub-picture pack headers are removed by the software demultiplexor. the decoder reads the header of the first packet (see figure 92 ) and jumps to the first display control sequence using the command pointer. figure 91 buffer management figure 92 sub-picture unit structure spuh (header) unused spu1 spu2 spu3 spun bit buffer base address (vid_spb) read pointer (vid_spread) write pointer vid_spwrite) bit buffer end address (vid_spe) 64-bit boundary pxd (pixel data) dcsqt (display control sequence table) spun (cont.) pxd position dcsq position wrap around h sub-picture bit map dcsq dcsq sub-picture data start bit map start next pts held in a register
c o n f i d e n t i a l 16 sub-picture decoder STI5518 152/294 7170179 d the instructions found in the dcsq packets enable the sub-picture unit to program the palettes, set mixing factors etc. for each region. the dcsq packets also contain a time stamp which indicates to which image the sub-picture information refers. this information is related to a local time for this sub-picture unit. the micro should enable a given sub-picture unit at the right global time via some registers: data buffer start position, start sub-picture unit status bit. the overall control of the sub-picture decoder is performed by software. the final information in the dcsq packet is the region size (rectangle) and the relative position, in bytes, of the bit-map start. a key point here is that the sub-picture decoder must read beyond the end of the dcsq packet in order to verify the next pts. with this information held in a register, the sub-picture decoder knows, in advance, when to change the dcsq or bit-map information. the sub-picture unit simply executes the same dcsq until the image corresponding to the next time-stamp is reached. this is done at the beginning of every field so that the sub-picture decoder can load all the relevant information from dcsq before the first sub-picture pixel is required. the sub-picture region declaration is held in registers in the decoder so that the sub-picture decoder is turned on and off at the correct position on the screen (see figure 93 ). the bit-map start-pointer indicates where, in the bit map data, to start decoding. when the correct image, corresponding to the local time stamp contained in the dcsq, should be displayed the sub-picture controller enables the sub-picture decode for that image. a pause mode is defined in the sub-picture decoder. as explained previously, the sub-picture decoder is autonomous within a sub-picture unit. this means that the dcsq switching is timed automatically using an internal 90 khz clock. during video trick modes, where the video stream may be frozen or slowed down the same thing should be possible with the sub-picture decoder in order to maintain the synchronization between the two streams. a pause mode is implemented for the sub-picture decoder which stops the 90 khz counter and therefore pauses the sub-picture decoder. this is controlled using the p field in the spd_ctl1 register and is synchronized to the vsync signal. this control bit can therefore be used as a pause and a single step control bit. the sub-picture decoder registers are put together in the sub-picture memory map except: sub-picture software reset (register spd_spr), sub-picture pause mode (spd_ctl1.p bit), sub-picture fifo full (bit 18 of vid_its and vid_sta register). figure 93 sub-picture region declaration spd_syd0 maximum 8 regions per line minimum 8 pixels spd_sxd0 spd_syd1 spd_sxd1
c o n f i d e n t i a l STI5518 16 sub-picture decoder 7170179 d 153/294 16.4 sub-picture display 16.4.1 look-up tables there are 11 look-up tables inside the sub-picture decoder: 1 highlight lut (2 bits to 4 bits mapping) 1 sub-picture lut (2 bits to 4 bits mapping) 8 pci luts (2 bits to 4 bits mapping) 1 main lut (4 bits to 24 bits mapping) the sub-picture and pci luts are automatically supplied by the decoder itself (sub-picture commands contained in the spu). the highlight and main luts need to be loaded by the st20 (spd_hcn, spd_hcol, spd_lut registers). the output of the sub-picture main lut is mixed with the other planes. the contrast value between these two sources is set by the set_contr dcsq command, by the pcinfs of a chg_colcon command or by a highlight color information (the highlight lut has the highest priority, followed by the pci luts. the sub-picture lut has the lowest priority). the mixed video is a 24 bits y, cr, cb video where: y mixed = [y planes x (16 - k) + y subp x k] / 16 cr mixed = [cr planes x (16 - k) + cr subp x k] / 16 cb mixed = [cb planes x (16 - k) + cb subp x k] / 16 k = 0 if contrast value from high light, sub-picture, pci luts = 0 k = contrast value + 1 if contrast value > 0 16.4.2 sub-picture areas the active sub-picture decoding area can be 720 x 576 or 720 x 480 pixels. in order to align the sub-picture decoding area with the video decoding area, the upper left corner of the active sub-picture decoding area has to be set by software, using the registers spd_xd0 and spd_yd0. the same semantics have been defined as for the video decoder, as shown in figure 94 . the active sub-picture display area is defined in a similar manner, using the spd_sxd0, spd_syd0, spd_sxd1 and spd_syd1 registers. the highlighted area is defined by spd_hls, spd_hlsy, spd_hlex, spd_hley registers, and is set by software. figure 94 sub-picture areas vertical blanking interval spd_yd0 spd_xd0 horizontal blanking interval sub-picture display area sub-picture decoding area spd_syd0 (0,0) spd_syd1 spd_sxd1 (0,575 or 479) (0,624 or 524) (0,863 or 857) spd_sxd0 (0,0)
c o n f i d e n t i a l 17 overlay graphics and texts STI5518 154/294 7170179 d 17 overlay graphics and texts 17.1 introduction the STI5518 has integrated ogt (overlay graphics and texts) hardware used for svcd. the data stream is similar to the sub-picture stream. the ogt bit stream is made up of ogt pages, where each page contains a header sequence followed by a bitmap packet (1 picture/page). ogt compressed data are stored in a bit-buffer with programmable position and size (in any multiple of 2 kbytes). the ogt decoder can decode a complete page of 2 fields in accordance with iec sc100b/np177/ptd-003 svcd specifications. the figure below illustrates the ogt model, with an ogt page placed in a screen and 2 highlight areas. 17.2 buffer management the bit-buffer is configured at reset. its size is defined by registers vid_spb and vid_spe and is constant during the decoding process.the ogt uses the following 4 sub-picture registers to control the ogt bit-buffer read and write proc- esses: vid_spb bit-buffer base address, programmed in units of 2 kbytes. vid_spe bit-buffer end address, programmed in units of 2 kbytes. vid_spread bit-buffer read pointer. this register must be updated with the vsync_bottom to re-decode the same ogt page, or to decode the next page. vsync_bottom is an offset to the st20 sdram base address, it is programmed in units of 64-bit words. vid_spwrite bit-buffer write pointer. this register must be set by the st20 before transferring each ogt page into the bit-buffer. the address is an offset to the st20 sdram base address, it is programmed in units of 64-bit words. figure 95 ogt display model screen display area (704x480) or (740x576) pixels ogt page area (width x height) top_line: left pixel highlights area1 highlights area 2 ogt_xdo,ogt_ydo. ogt_sxdo,ogt_sydo spd_hlxs, spd_hlys ogt_hl2xo,ogt_hl2yo
c o n f i d e n t i a l STI5518 17 overlay graphics and texts 7170179 d 155/294 17.3 operation ogt page data are sent via the sub-picture data fifo to the ogt decoder. the fifo is written to by dma or by cpu write. only bit-map data are transferred into the bit-buffer. the parameters contained into the ogt header (areas, highlight, lut,) are extracted by software and are held in the ogt registers. each ogt page contains an associated presentation time stamp (pts) which controls when the ogt page is dis- played. when the pts is reached, the register ogt_ctl.s (start_decode) is set and register vid_spread is pro- grammed on the vsync, before the vsync_top where the ogt page is displayed. the ogt decoder displays the same page until the next pts, or until the display time (defined by the duration time) is reached. to re-decode and re-display the same page, the read pointer must be reprogrammed and register bit ogt_ctl.s must be set to 1 before each vsync top. to stop the display, ogt_ctl.s must be reset before the vsync_top , where the ? pts + duration ? time is reached. 17.4 display the ogt decoder contains 3 look-up tables: one ogt and two highlight. the clut defines 4 color and transparency values for the pixels of the ogt page. the clut can be changed from page to page. the highlight and main lut are loaded by registers ogt_lut, ogt_lut_h1, ogt_lut_h2. the active ogt decoding area can be 704x576 or 70x480 pixels. to align the ogt decoding area with the video decoding area, the upper left corner of the active ogt area must be set by software using the registers ogt_xdi and oct_ydi. the active ogt decoding area is defined by registers spd_sxdo, spd_sydo, spd_sxd1 and spd_syd1. 2 highlight areas can be defined in each ogt area. however, the bottom of the highlight1 area must always be above the top of the highlight2 area. the position of highlight1 is defined by registers sdp_hlsx, spd_hlsy, spd_hlex, spd_hley; the position of highlight2 is defined by registers ogt_hl2xo, ogt_hl2yo, ogt_hl2y1, ogt_hl2x1.
c o n f i d e n t i a l 18 display planes STI5518 156/294 7170179 d 18 display planes 18.1 overview the graphics and display subsystem reads, processes, overlays and mixes pixel data stored in the various buffers of the sdram, and produces a combined image for display on a tv. the buffers are called display planes. the graphics and display subsystem has four display planes as listed and illustrated below: background color ( background color plane on page 157 ); mpeg video plane ( mpeg video plane on page 158 ); on-screen display plane ( on-screen display (osd) on page 169 ); sub-picture plane ( sub-picture or cursor plane on page 183 ). the display planes are normally overlaid in the order shown above, with the background color at the back and the sub- picture used as a cursor plane at the front. the position of the sub-picture plane is programmable through bit vid_out.spo. it can be configured to be: the most forward layer, as shown above; in this case it can be used as a cursor plane or a second on-screen display plane. behind the osd plane, in front of the mpeg video. in this case it can be used as a second on-screen display plane. figure 96 display planes on-screen display 08:23pm replay score stats replay score stats sub-picture plane 08:23pm replay score stats 08:23pm decompressed video overlaid planes background color
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 157/294 figure 97 shows a simplified block diagram of the graphics and display subsystem. the planes can be blended together using the mixing unit, as described in mixing display planes on page 183 . the mixing unit has two outputs as illustrated in the figure above: a 4:2:2 output that is input to the denc to generate cvbs and yc output. this format is generally used for vcr recording. the osd and sub-picture display planes can be disabled from this output as described in on page 185 . a 4:4:4 output, used in either of the following ways: as an input to the denc to generate the yuv and rgb signals. this is generally used for tv display, and includes all of the available display planes. as a digital signal that bypasses the denc and is output to the yuv pins ? yc0 to yc7 ? . this signal is downsampled to 4:2:2 format by removing the chroma. it is used, for example, for connection to an external graphics device. the routing of the 4:4:2 and 4:4:4 signals from the mixing unit, through the denc to the dacs, is controlled by the den_cfg2 and den_cfg8 registers. when the ycrcb 4:4:2 signal is used, the presence of osd in the denc output is selected or deselected by the osd block header format field s (see table 85: osd block header format on page 177 ). when the ycrcb 4:4:4 signal is used, osd is always present in the denc output. 18.2 background color plane the background color plane has the same size and position as the mpeg video plane. this plane is always at the back with all the other display planes on top. the color of the plane is defined by three registers: vid_bck_y, vid_bck_u and vid_bck_v. figure 97 graphics and display subsystem 16 sdram emi video decoder 1d block move engine denc mixing 4:2:2 vertical processor horizontal src osd sub-picture decoder 4:2:2 4:4:4 4:4:4 4:4:4 sdram block to row mux 4:2:0 unit ycrcb 4:2:2 digital output down sample to 4:2:2 4:4:4 cvbs & yc yuv &rgb den_cfg2 den_cfg8 presence of osd in the denc output is set here by the osd block header format field s syncro etu656 &601 sdram bus & arbiter
c o n f i d e n t i a l 18 display planes STI5518 158/294 7170179 d 18.3 mpeg video plane the mpeg video plane displays a moving image decoded from an mpeg video stream by the mpeg video decoder. the display priority has the mpeg video as the third layer, on top of the background color. the sub-picture and osd output are on top of the mpeg video plane. the picture data is received either from the display frame buffer area of the external memory, or directly from the mpeg video decoder in the case of b frames in memory reduction mode. the data is passed through three fifos (one for luminance and two for chrominance) into the block-to-row converter. the block-to-row converter generates a line based raster from the frame store, which is organized as mpeg macroblock. it also performs the pan/scan operation and vertical post-processing of the decoded video. the block-to- row converter is described in section 18.3.3. the output of the block-to-row converter is fed to the sample rate converter (src). the src is an 8-tap filter, which has two functions: up and down scaling of pel data when the displayed line length is greater or smaller than the decoded picture width, and implementation of the fractional part of the pan-scan horizontal offset. the outputs from the src are upsampled lines each having equal numbers of luminance and chrominance samples. the src can be bypassed if desired. the sample rate converter is described in sample rate converter on page 159 . 18.3.1 setting-up the display the vid_dfp and vid_dfc registers must be set up with the base address of the buffer containing the picture to be displayed. this register is double-buffered; when a new value is written it is taken into account on the occurrence of a vsync. thus it is possible to write a new value for this pointer every field, although it would normally be updated only once per frame. the picture stored in the buffer is always treated as a frame by the STI5518. if at any time no display is required, bit vid_dcf.evd may be reset, in which case a constant black value is output. the size and location of the display window is defined by the registers vid_xdo, vid_xds, vid_ydo and vid_yds. the values loaded into these registers define the horizontal and vertical boundaries of the displayed picture, as shown in figure 98 . figure 98 display window positioning decoded picture display vid_ydo vid_xdo vid_xds vid_yds background color border
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 159/294 18.3.2 sample rate converter the purpose of the sample rate converter (src) is to allow up or down sampling of picture data in order to increase or decrease the number of horizontal samples in a line. upsampling is necessary if the horizontal size of the display is greater than the decoded picture width. for example if it is required to display a 720-pel wide 16:9 source image on a 4:3 display also of 720-pel width, then 540 pels selected from each source line must be upsampled to 720. downsampling is required when the resolution of the display is less than that of the decoded image. for example when square pixels are required for an ntsc image the 720 pixel wide image decoded must be downsampled to 640 pixels. to enable the src, bit vid_dcf.dsr must be reset. if this bit is set, the src is bypassed and the horizontal resolution of the decoded picture is not changed. the sample rate converter can change the sampling rate by a programmable factor. the upsampling ratio is limited to 8 and the downsampling to less than or equal to a factor of 2. the same filter is used both for upsampling and downsampling. as either of these limits is approached artifacts may appear in the displayed image. the src operates by directly interpolating samples required for the new sampling rate by using those of the decoded picture data read from the display buffer. this is performed by an 8-tap interpolation filter with the structure shown in figure 99 . the filter has three sets of delay registers multiplexed between the y, c b and c r samples. it has 8 sets of coefficients, each set defining one of 8 sub-pel interpolation positions. consider an upsampling example, for sub-pel position 0, the output is aligned with stored sample ? r4 ? , for sub-pel position 1, the output corresponds to an interpolated pel position one eighth of the distance from sample ? r4 ? to sample ? r5 ? , and so on. the number of inputs clocked into the src is equal to the number of samples used in each line of the source image, and the number of outputs generated is equal to the number of samples displayed. thus the rate of generation of outputs will be greater than the input data rate in the case of upsampling and less in the case of downsampling. figure 99 8-tap interpolation filter r7 c1 r6 c2 r5 c3 r4 c4 r3 c5 r2 c6 r1 c7 r8 c0 input from display buffer (0, 1 or 2 samples) x(n ? ) delay registers new input output to vertical filter y(m ? )
c o n f i d e n t i a l 18 display planes STI5518 160/294 7170179 d operation of the src the sample rate converter works in the following manner: the src takes block of m samples of the input signal denoted as x(n ? ), n ? = 0,1,2,3,.... m-1. and computes a block of l output samples y(m ? ), m ? = 0,1,2,. l-1. for each output sample time m ? , m ? = 0,1,2.., l-1 the 8 samples in the filter are multiplied with one of the 8 sets of filter coefficients the products are accumulated to give the output y(m ? ). each time the quantity m ? m/l increases by one, one sample from the input buffer is shifted into the filter. the coefficient set used will depend on the position of the sample being generated relative to the original samples of the source image. thus after l output values are computed m input samples have been shifted into the filter delay registers. the src up/down sampling factor is set up in the vid_lsr register. the re-sampling factors for the luminance and chrominance components are exactly the same. the resampling factor is equal to l/m. the value programmed into vid_lsr is 256 m/l. this value is used to determine both the rate of input of data into the filters and the sequence of sub-pel interpolation positions. the mechanism by which this is achieved is shown in figure 100 . upsampling example the example in figure 101 illustrates the operation of the sample rate converter when the upsampling ratio is 8:7. for every 8 samples clocked out of the filters, 7 samples are clocked in. to illustrate the interpolation positions, at the right of figure 101 are shown the outputs which would occur with a simple linear interpolation (i.e.a 2-tap filter). the actual src output values are the 8-tap filter outputs with coefficients figure 100 10-bit adder new input sub-pel position initialize start lsr
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 161/294 appropriate to sub-pel positions 0, 7, 6, 5, 4, 3, 2, 1, 0 etc. the src output is limited to lie within the range [1,254], so the codes 0x00 and 0xff are never output, giving compatibility with itu-r 656. the vid_lsr value is added into an accumulator register at a rate equal to the filter output rate. the top two bits indicate how many new inputs are to be loaded into the filter (0,1 or 2). the next three bits of the accumulator register are used to select the sub-pel position. for example, with an upsampling factor of 8:7, the vid_lsr value is (256/8) 7 = 224. the sequence of values in the accumulator register will be as shown in table 74 , assuming that it is initialized to zero. figure 101 src example for 8:7 upsampling accumulator register new input sub-pel position 0yes0 224 no 7 192 yes 6 160 yes 5 128 yes 4 96 yes 3 64 yes 2 32 yes 1 0yes0 table 74 accumulator register sequence for upsampling example a - relation of input and output samples input output sub-pel position 07 6543210 b - filter operation n+7 n+3 n+6 n+5 n+10 n+4 n+2 n+1 n+7 n+3 n+6 n+5 n+4 n+2 n+1 n+7 n+3 n+6 n+5 n+4 n+2 n+1 n+8 n+9 n+11 n+12 n+13 n+14 n+7 n+3 n+6 n+5 n+4 n+2 n+8 n+9 n+7 n+3 n+6 n+5 n+4 n+8 n+10 n+9 n+7 n+6 n+5 n+4 n+8 n+11 n+10 n+9 n+7 n+6 n+5 n+8 n+12 n+11 n+10 n+9 n+7 n+6 n+8 n+13 n+12 n+11 n+10 n+9 n+7 n+8 n n r8 r7 r6 r5 r4 r3 r2 r1 delay register contents (one cycle per output clock cycle) no input sample read 3/4 (n+5) +1/4 (n+4) 5/8 (n+6) +3/8 (n+5) 1/2 (n+7) +1/2 (n+6) 3/8 (n+8) +5/8 (n+7) 1/4 (n+9) +3/4 (n+8) 1/8 (n+10) +7/8 (n+9) n+10 n+3 7/8 (n+4) + 1/8 (n+3) output (shown interpolated linearly)
c o n f i d e n t i a l 18 display planes STI5518 162/294 7170179 d the vid_lsr value thus defines a cycle of sub-pel positions as well as the rate of data input. if a value of less than 32 is loaded into vid_lsr, i.e. an upsampling ratio of greater than 8 is defined, there could be repeated values in the filter output. this may cause unacceptable display artifacts. downsampling example the example shown in figure 102 illustrates the operation of the sample rate converter when the downsampling ratio is 9:8 (720:640). the vid_lsr value required for a downsampling ratio of 9:8 is 256 x 9 /8 = 288. figure 102 src example for 9:8 downsampling accumulator register number of inputs sub-pel position 010 288 1 1 576 1 2 864 1 3 128 1 4 416 1 5 704 1 6 992 1 7 020 table 75 accumulator register sequence for downsampling example a - relation of input and output samples input output sub-pel position 01 2345670 b - filter operation n+7 n+3 n+6 n+5 n+10 n+4 n+2 n+1 n+7 n+3 n+6 n+5 n+4 n+2 n+1 n+8 n+9 n+11 n+12 n+13 n+14 n+7 n+3 n+6 n+5 n+4 n+2 n+8 n+9 n+7 n+3 n+6 n+5 n+4 n+8 n+10 n+9 n+7 n+6 n+5 n+4 n+8 n+11 n+10 n+9 n+7 n+6 n+5 n+8 n+12 n+11 n+10 n+9 n+7 n+6 n+8 n+13 n+12 n+11 n+10 n+9 n+7 n+8 n r8 r7 r6 r5 r4 r3 r2 r1 delay register contents (one cycle per output clock cycle) 1/4 (n+6) +3/4 (n+5) 3/8 (n+7) +5/8 (n+6) 1/2 (n+8) +1/2 (n+7) 5/8 (n+9) +3/8 (n+8) 3/4 (n+10) +1/4 (n+9) 7/8 (n+11) +1/8 (n+10) n+11 n+3 1/8 (n+5) +7/8 (n+4) output (shown interpolated linearly) n+14 n+13 n+12 n+11 n+10 n+9 n+8 n+15
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 163/294 at the start of a line, the 3 sets of delay registers r1, r2 and r3 are loaded with the black value (y=16, c b =c r =128). the first output is thus derived from the inputs stored in registers r4 to r8. at the end of a line, the last eight input samples are stored in registers r1 to r8. the last valid interpolation is between the samples stored in r4 and r5. correct interpolation is not possible beyond this except in the case where the next output is in sub-pel position 0. this output is valid since coefficient c0 is zero for this position and the invalid sample beyond the end of the line is ignored. there is thus no valid interpolation possible between the last four input samples. this is illustrated in figure 103 in which 544 pels are upsampled to 721, in which the upsampling ratio is 4:3. the vid_lsr register would be loaded with the value 192. the number of valid outputs generated can be calculated as follows: the ratio between the number of input and output samples is 256: vid_lsr . given that the last output sample cannot occupy a position beyond the fourth-last input sample, the following inequality is always true: vid_lsr (n-1) 256 (m-4) where n is the number of output samples and m is the number of input samples. the value of n is thus given by: n = ? 256 (m-4) / vid_lsr + 1 ? where ? x ? indicates the integer part of x. the value programmed into the vid_xds register must ensure that all samples beyond the last valid sample are masked. 18.3.3 block-to-row converter the block-to-row converter generates a line-based raster scan of individual video components (ycbcr) from an mpeg macroblock-organized frame store. the block-to-row converter also performs: pan/scan; vertical post-processing of decoded video, such as: vertical zoom-out x2, x3, x4 vertical programmable filtering with any zoom-in, and zoom-out up to x2; figure 103 downsampling example input output start of line 12 345 6 12 345 input output end of line 717 718 719 720 721 538 539 540 541 542 543 544 last valid output (sub-pel position 0)
c o n f i d e n t i a l 18 display planes STI5518 164/294 7170179 d horizontal zoom-out x2 (for zoom-out by more than x2). pan/scan vectors when the display window has a smaller horizontal dimension than the decoded picture, a vector can be programmed in order to define the starting point of the displayed picture, as shown in figure 104 . the vertical component must be macroblock aligned, so the line number must be a multiple of 16. this vector defines the point in the decoded picture which corresponds to the top-left-hand corner of the displayed picture. the displayed picture size and location is defined by the numbers programmed in registers vid_xdo, vid_xds, vid_ydo and vid_yds. the pan/scan vector components are programmed into the registers vid_pan, vid_lso, vid_cso and vid_scn. these registers are double-buffered; when a new value is written it is taken into account on the occurrence of a vsync. thus it is possible to write a new value of the pan/scan vector for every field. the integer part of the horizontal component of the pan/scan vector is loaded into the vid_pan register, and the fractional part defines the contents of the vid_lso and vid_cso registers. the relationship between these quantities is illustrated in figure 105 . the numbers loaded into the vid_lso and vid_cso registers are used to initialize the luminance and chrominance upsampling control registers at the start of every line. vid_lso is set up directly with the value of the fractional part of the pan/scan vector horizontal component. vid_cso is set up with half of this number, plus 128 if the integer part is an odd number. the resolution to which the horizontal component can be defined is 1/8 pel. the vertical component of the pan/scan vector is programmed into vid_scn, in units of macroblock rows (i.e. units of 16 lines). scanning can done line-by-line on any of the 8 lines in each field, by programing the off even and offodd bits of the vid_vfcmode and vid_vflmode registers. figure 104 pan/scan vector figure 105 components of the pan/scan vector decoded picture displayed picture vector luma chroma decoded displayed chroma luma vid_lso vid_pan vid_cso pan vector
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 165/294 vertical filter the block-to-row converter has an output filter for vertical post-processing of the video. this vertical filter performs the chroma reconstruction from 4:2:0 to 4:2:2 format, and upsamples and downsamples the luma and chroma components. any zoom, from any zoom-in to zoom-out by 4, can be performed in addition to the following basic modes zoom-in by 2; zoom-out by 2, 3 or 4 (zoom-out by 4 must be set by register bit vid_dcf.zoom4); zoom-out by n (where n lines are produced for each line stored, 1/16 n 2); 16:9 and 14:9 letter box filtering. the programmable pal/ntsc vertical filter optimizes video quality according to the type of source - full or half resolution, interlaced or progressive. one luma filter operation and one chroma filter operation can run at the same time. the chroma filter mode is programmed in the vid_vfcmode register, and the luma filter mode is programmed in the vid_vflmode register. this table describes the function of these registers and table 76 on page 167 lists the recommended configurations. here are the vid_vflmode and vid_vfcmode i program for the zoomout by 3 in full progressive and half progressive source resolution. the interface between the block-to-row converter and the next block (horizontal sample rate converter (src)), has three video components. the video data output is in 4:2:2 format. successive samples are presented at the relevant video component port (y, c r or c b ) synchronously with the relevant output sample clocking signal. bitfield description increment the increment bit is used for downsampling up to zoom-out x2, and in conjunction with zoomout for fractional zoom-out between x2-x3, or x3-x4, for example x2.1, x2.2... etc. define the vertical ratio of the zoom, and given by the formula: where framestoresize is the number of lines in the framestore, and desiredsize is the number of lines in the display region. ex, to display a 525 line framestore onto a 625 display region: offeven vertical scans for even fields. adjusts and superposes the luma and chroma filtering. the offset is a variable distance from the first line. offodd vertical scans for odd fields. adjusts and superposes the luma and chroma filtering. the offset is a variable distance from the first line. zoomout the increment bit is used for downsampling up to zoom-out x2, for zoom-out x3 and x4, zoomout must be used in as below. for zoom-out between x2-x3, or x3-x4, for example x2.1, x2.2... etc. zoo- mout must be used in conjunction with increment. 00: zoom-out up to x2 01: zoom-out by 2 10: zoom-out by 3 11: zoom-out by 4 intp interpolation field forces line repeat instead of integration (if 0, the top-line value is reproduced). horizdn horizontal downsample by 2; neighboring samples are averaged. note: that no other post processing filter can be used at the same time as this function. the lines in the macroblock buffer ram are read out as they are, however, the line offset part of start_offset is still used. increment framestoresize desiredsize --------------------------------------- 5 1 2 ?? ?? 1 ? = increment 525 625 -------- -512 ?? ?? 1 ? 429 ==
c o n f i d e n t i a l 18 display planes STI5518 166/294 7170179 d horizontal compression for zoom-out by three or four, a frame store must not only be compressed vertically by three or four, but also horizontally by three or four. the src is able to downsample up to a factor of two. for zoom-out by three or four horizontally, the block-to-row converter must pre-process its output data for the src. this is set by bit 39 of the vid_vfcmode and vid_vflmode registers.
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 167/294 filter modes the vertical filter supports an unlimited number of configurations, however, recommended configurations are listed in the table below. display source resolution luminance reg. (vid_vflmode) chrominance reg. (vid_vfcmode) vid_dcf spacial temporal [39] [38] [37:36] [35:23] [22:10] [9:0] [39] [38] [37:36] [35:23] [22:10] [9:0] [1] [0] horiz down interpolate zoom-out offset odd offset even increment horiz down interpolate zoom-out offset odd offset even increment lfb cfb full screen full interlaced or progressive 0 1 00 255 255 509 0 1 00 0 0 254 0 0 interlaced or progressive 00000 0 51100000 0 25500 progressive01000 0 51101000 0 51101 half interlaced or progressive 0 1 00 255 127 253 0 1 00 0 0 126 0 0 progressive 0 0 00 127 0 511 0 0 00 0 0 255 1 1 16:9 letter box full interlaced or progressive 0 1 00 255 255 679 0 1 00 0 0 339 0 0 progressive 0 1 01 255 0 679 0 1 01 0 0 339 1 1 half interlaced 0 1 00 255 127 339 0 1 00 0 0 169 0 0 progressive 0 1 00 127 0 679 0 1 00 0 0 339 1 1 14:9 letter box full interlaced (field based) 0 1 00 0 36 583 0 1 00 0 0 291 0 0 480 to 576 full interlaced/pr. 0 1 00 512 469 425 0 1 00 192 42 212 0 0 576 to 480 full interlaced/pr. 0 1 00 512 563 611 0 1 00 192 90 305 0 0 zoom-in x 2 full interlaced or progressive 0 1 00 0 127 255 0 1 00 192 0 127 0 0 full progressive 0 1 00 256 191 511 0 1 00 0 0 255 1 1 zoom-in x4 full interlaced 0 1 00 255 511 127 0 1 00 0 0 63 0 0 zoom-in x4 half interlaced 0 1 00 255 288 63 0 1 00 0 0 31 0 0 zoom-in x2 half progressive 0 1 00 128 0 255 0 1 00 0 0 127 1 1 zoom-out x2 full interlaced/ progressive 01000 0 101901000 0 50900 half interlaced 0 1 00 255 255 509 0 1 00 0 0 253 0 0 half progressive 0 1 01 127 0 509 0 1 00 0 0 509 1 1 zoom-out x3 full interlaced/ progressive 10100 0 57310010 0 38200 half interlaced 0 1 01 0 0 380 0 1 00 0 0 380 0 0 half progressive 0 0 10 0 0 573 0 0 01 0 0 382 1 1 zoom-out x4 full interlaced/ progressive 10110 0 50910110 0 25400 half interlaced 0 1 00 0 0 1019 0 1 00 0 0 509 0 0 half progressive 0 0 11 255 64 507 0 0 11 0 0 253 1 1 table 76 vertical filter modes
c o n f i d e n t i a l 18 display planes STI5518 168/294 7170179 d figure 106 filter mode examples a b c d e f g h a a b b c c d d e e f f g g h h a b c d e f g h a b c d e f g h no zoom-out parameter value start_offset_odd 000000000 start_offset_even 000000000 increm ent 0111111111 interpolate don ? t care 1 zoom_out_mode 00 horizontal_downsample 0 increment 255 offset 0 no interpolation parameter value start_offset_odd 000000000 start_offset_even 000000000 increment 0011111111 interpolate 0 zoom_out_mode 00 horizontal_downsample 0 a b c d e f g h a (4a+4b)/8 b (4b+4c)/8 c (4c+4d)/8 d (4d+4e)/8 e (4e+4f)/8 f (4f+4g)/8 g (4g+4h)/8 h (4h+4i)/8 increment 255 offset 0 parameter value start_offset_odd 000000000 start_offset_even 000000000 increment 0011111111 interpolate 1 zoom_out_mode 00 horizontal_downsample 0
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 169/294 18.3.4 degradation mode in certain situations the system constraints may justify use of the STI5518 in a configuration where the available bandwidth on the sdram interface is limited. there could be many reasons for these constraints, such as a low clock frequency to use cheaper sdrams, or the processor making heavy use of the sdram. mpeg decode and display, being a real-time process and also a heavy user of sdram memory bandwidth, will then require a graceful degradation mode. the effective distance (in pixels) between the display process and the decode process is measured by hardware. in conditions of limited bandwidth the decoder will become late and therefore may get caught by the real-time limited display process. degradation mode can be enabled or disabled using the panic threshold register vid_pth. a threshold or minimum allowable distance between the decode and display processes can be set. if this threshold is crossed, the decoder will automatically ensure that any bidirectionally predicted macroblock access will result in only a single prediction access to external memory, thus reducing the bandwidth required by the decoder, and allowing recovery. 18.4 on-screen display (osd) the STI5518 has an integrated on-screen display (osd) unit. this can be used to overlay the video picture with graphics generated by software. the display priority puts the osd in front of the mpeg video. it can be configured to be either in front of or behind the sub-picture plane by clearing or setting vid_out.spo respectively. the osd can be enabled by setting osd_cfg.ena. the osd bit-map is defined with respect to the display area and is independent of the decoded picture size and any pan/scan offset. the output from the osd is in 4:4:4 format. the osd of the STI5518 has the following special features: linked-list memory management; selectable 2, 4 or 8-bits per pixel palette modes giving 4, 16 or 256 palette colors; either 6-bit luma resolution and 4-bit chroma resolution per component or 8-bit luma resolution and 8-bit chroma resolution; programmable 4-bit mixing factor for each osd region to blend the video plane and osd data; when anti-aliasing is enabled, each color in an osd region can be assigned a separate 6-bit mixing factor for mixing with video; optional anti-flicker and anti-flutter filters; half resolution mode. these features are described in the following sections. the osd unit uses color look-up-tables (luts), also called palettes , with 2-bit, 4-bit or 8-bit input. the lut means that memory is used efficiently when only a few colors are needed. a 2-bit lut means that four colors can be used at once, and each pixel of the bit-map occupies only two bits of memory. a 4-bit lut gives 16 colors and an 8-bit lut gives 256 colors. the palette of 4, 16 or 256 predefined colors is loaded into the sdram by software using the shared memory interface. the palette modes are described in section 18.4.5. the output from the lut can be 14-bit pixels (6-bit y, 4-bit cb, 4-bit cr) or 24-bit pixels (8-bit y, 8-bit cb, 8-bit cr) plus one bit or six bits for transparency control. the color modes are described in section 18.4.5. the osd can consist of a number of display regions, each with its own palette and characteristics. the number of osd regions resident in memory at any time is limited only by the amount of memory available. each region has a specification, stored in memory, which contains a header, possibly including a palette, and a bit-map. the specifications for the regions are linked in a list structure. the bit-map data in each specification is contiguous with the palette
c o n f i d e n t i a l 18 display planes STI5518 170/294 7170179 d information, as shown in figure 112: osd specification on page 173 . the bit-map refers to the 2-, 4- or 8-bit color definitions in the palette to create the required picture. during the display of an image a small state machine first picks up the palette from sdram and loads it into the lut then the osd region start and stop addresses are read. when the display reaches the osd start position (defined in the bit-map) the bit-map is sent pixel by pixel to the lut and the display switches from video to the output of the lut or a mixture of both. this process continues until the defined stop position. thus, for the defined osd region, the video display is overlaid by the colors which are defined by a combination of the lut and the bit-map. 18.4.1 using the osd the osd is enabled if bit osd_cfg.ena is set. the starting address in memory of the osd specification for the top field is defined by register vid_otp, and that for the bottom field is defined by register vid_obp. the line numbers used to define the top and bottom of an osd region are the internal (field) line numbers defined in figure 107 . it is thus possible to share the same osd specification for both fields of a frame. in this case the vid_otp and vid_obp registers would be loaded with the same address. osd specifications can be written into the sdram using the st20 or the block move dma. they can be rapidly moved within sdram using the sdram block move function. 18.4.2 osd regions the osd function can be used to display a user-defined bit-map over any part of the displayable (i.e. non-blanked) screen, independent of the size and location of the active video area (defined by vid_xdo, vid_xds, vid_ydo, vid_yds). this bit-map can be defined independently for each field. figure 107 internal line numbering 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 top field bottom field b/t hsync b/t hsync
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 171/294 the osd consists of one or more regions in the display. each region is a rectangle, and can have its own palette and other properties. figure 108 shows examples of osd regions. region 3 shows that the osd can be outside the active video area. no display line can be included in more than one active osd region, so only one osd region can be active on a line. if two areas of osd are required which include the same display line then one region must be defined which includes both areas. for example, figure 109 shows two areas, marked a and b, with some display lines used in both areas. if these areas are to be active at the same time then one region, marked c, must be defined, which includes both areas. the area of c outside a and b can be defined as transparent. 18.4.3 osd specification an osd specification is two lists of blocks of 64-bit words, stored in sdram. one list is for the top field and one for the bottom. generally the lists are linked lists, as shown in figure 110 . the order of the blocks in the list is the order of the regions from top to bottom of the display. the last block in an osd specification must point to an invalid header, which figure 108 osd regions figure 109 boundary of displayable area active video area (x 0 , y 0 ) (x 1 , y 1 ) region 1 region 2 transparent region 3 a b c areas of osd osd region display lines in both areas
c o n f i d e n t i a l 18 display planes STI5518 172/294 7170179 d gives a starting line beyond the displayable area (example oxffffffffffffffff). this invalid header will end the osd. the only case in which linked lists are not used is when the palette mode is 2 bits for 2 pels, i.e. the palette mode flags are set to m=1, q=1, e=0, as described in section 18.4.5. in this case the blocks must be contiguous in memory, so the start of each block must immediately follow in memory the end of the previous block, as shown in figure 111 . no linked list is allowed after a 2 bits for 2 pels zone. figure 110 linked list structure for osd data figure 111 block structure for osd data in 2 bits per 2 pixels mode osd1 top field block osd2 top field block osd3 top field block osd3 osd2 osd1 decoded image osd1 bottom field block osd2 bottom field block osd3 bottom field block linked list of linked list of vid_otp vid_obp bottom field blocks top field blocks invalid header invalid header osd1 top field block osd2 top field block osd3 top field block osd3 osd2 osd1 decoded image osd1 bottom field block osd2 bottom field block osd3 bottom field block linked list of linked list of vid_otp vid_obp bottom field blocks top field blocks invalid header invalid header
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 173/294 each block defines one field of one region and includes a header, an optional palette and a bit-map. each block must be aligned on a 64-bit boundary and the first block of each field must be aligned on a 256-bit boundary. figure 112 shows a linked list of two osd blocks. each region has associated with it a palette defining 4, 16 or 256 colors, used by the bit-map. if required, one of these colors can be ? transparent ? , allowing the background to show through. each region may have its own palette, or if a sequence of regions uses the same palette then the palette need only be defined in the first region of the sequence. the header of each block contains a definition of the boundaries of the region, a pointer to the next region and other control information. the format of the palette depends on the palette mode, as described in section 18.4.5. the formats are given in section 18.4.7. 18.4.4 osd region position the position of each region of the osd is defined in the header of the specification block. the positions of the left and right edge samples of an osd region are defined as follows, in units of pixclk cycles from the falling edge of hsync : left edge position = (2 x_left ) + 8 right edge position = (2 x_right ) + 9 figure 112 osd specification header palette bit-map data region 1 header palette bit-map data region 2 null header line
c o n f i d e n t i a l 18 display planes STI5518 174/294 7170179 d where x_left and x_right are the values defined in the header of the osd region specification. this is illustrated in figure 113 and figure 114 . the first sample output in an osd region is always a c b value. the top and bottom of the region are defined by the values y_top and y_bottom , which are also in the block header. these values are specified in units of display lines. the top line specified in the first word of an osd region specification must be greater than or equal to 3. 18.4.5 color palette each specification block after the first can either define a new palette or use the same palette as the preceding region. if a new palette is defined then it is held in sdram immediately after the header and before the bit-map. the p flag in the header defines whether the palette follows the header, as shown in table 77 palette modes the palette mode defines the bits per pel in the bit-map and the pixel resolution. the palette mode can be different for each osd region, and is defined by the m, q and e flags in the osd region specification header. q defines the pixel figure 113 osd region horizontal positioning in 4:4:4 output figure 114 osd region horizontal positioning in 4:2:2 output p palette 0 the palette for the region is immediately after header. 1 the palette is the same as for the preceding region. table77palette as before flag y y y y y y 2 (x_right - x_left) + 2 chroma samples or (x_right - x_left) + 1 pels 2x_left + 7 chroma samples hsync cb cr cb cr cb cr cb cr cb cr cb cr chroma sample number 2x_left + 8 chroma sample number 2x_right + 10 cb y cr y cb y cr y cb y cr y 2 (x_right - x_left) + 2 samples or (x_right - x_left) + 1 pels sample number 2x_left + 8 sample number 2x_right + 9 2x_left + 7 samples hsync
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 175/294 resolution, allowing half resolution modes to save memory while retaining the color resolution. the meaning of each combination of these flags is given in the table below to reduce the size of the bit maps while retaining the color resolution, a half resolution mode is provided, as shown in in half resolution, each pel in the bit-map defines the color of two adjacent pixels in the same line in the display. color modes the pixel color mode defines the format of the output from the palette. three pixel color modes are supported, as listed in in the table below. this table shows how many bits are used for each color element and how many bits for the mixing factor mixweight, which determines the effect of overlaying the picture. anti-aliasing is supported only with 24-bit color. 24-bit or 14-bit color for the region field is selected by the bit tc in the header of the specification block. anti-aliasing i s selected by the bit aa in the header. the format of each line of the palette depends on the color mode. the table below gives the format of the palette lines for each color mode. m q e bits per pixel no. of colors resolution 000241 pel 110242 pels 1004161 pel 0104162 pels 00182561 pel 11182562 pels 101reserved 011reserved table 78 m, q and e palette mode header flags mode color resolution mixing reference 24-bit color with anti-aliasing y[7:0], cb[7:0], cr[7:0] mixweight[5:0] defined for each color. table 80 24-bit color y[7:0], cb[7:0], cr[7:0] mixweight[3:0] defined for the region. table 80 14-bit color y[5:0], cb[3:0], cr[3:0] mixweight[3:0] defined for the region. table 81 table 79 osd color modes field bits description cr[7:0] 7:0 cr chroma value cb[7:0] 15:8 cb chroma value y[7:0] 23:16 y luma value w[5:0] 29:24 mix weight. see section 18.4.9. reserved 31:30 reserved. write 0. table 80 palette line format in 24-bit color with anti-aliasing field bits description cr[7:0] 7:0 cr chroma value cb[7:0] 15:8 cb chroma value y[7:0] 23:16 y luma value table 81 palette line format in 24-bit color without anti-aliasing
c o n f i d e n t i a l 18 display planes STI5518 176/294 7170179 d standard colors the table below shows the 14-bit y, c r and c b values nearest to the standard color bar colors. the table below shows the 24-bit y, c r and c b values nearest to the standard color bar colors. t 24 transparency 0 do not blend video with osd for this color. 1 blend video with osd for this color using the mix weight. reserved 31:25 reserved. write 0 field bits description cr[3:0] 3:0 cr chroma value cb[3:0] 7:4 cb chroma value t 8 transparency: 0 do not blend video with osd for this color. 1 blend video with osd for his color using the mix weight. reserved 9 reserved. write 0. y[5:0] 15:10 y luma value table 82 palette line format in 14-bit color mode standard color y c r c b white 0x3b 0x8 0x8 black 0x04 0x8 0x8 red 0x10 0xd 0x6 green 0x1c 0x4 0x4 blue 0x9 0x7 0xd yellow 0x28 0x9 0x3 cyan 0x22 0x3 0xa magenta 0x15 0xc 0xd table 83 standard colors in 14-bit color standard color y c r c b white 0xec 0x80 0x80 black 0x100x800x80 red 0x40 0xd4 0x64 green 0x70 0x40 0x48 blue 0x24 0x74 0xd4 yellow 0xa0 0x8c 0x2c cyan 0x88 0x2c 0x9c magenta 0x54 0xc8 0xb8 table 84 standard colors in 24-bit color field bits description table 81 palette line format in 24-bit color without anti-aliasing
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 177/294 18.4.6 osd bit-map the bit-map for an osd region follows the palette if defined or the header if no palette is defined. the bit-map defines the osd pixels in left to right order within lines, and the lines in top to bottom order. the number of bits per pixel may be 2, 4 or 8 depending on the palette mode. the value for each pixel gives the line of the palette which defines the color for the pixel. as all the different sources are mixed in 4:4:4 format, there is no risk of mis-colored boundary between osd, video and sub-picture. an homogeneous decimation is applied to avoid the problem on the 4:2:2 format. 18.4.7 osd block header format ta b le 8 1 shows the layout of the header, which occupies one 64-bit word. table 85 shows the layout in graphical form, with each line representing a quarter of a 64-bit word. the header contains the pointer osdp[18:0]. this pointer defines the address of the next block in the linked list to load from memory, as described in section 18.4.3. the blocks can be anywhere in sdram and the pointer is given in units of 64-bit words. the block must be 16-word aligned, so the pointer osdp[18:0] must be a multiple of 16. thus the least significant 4 bits of osdp are always zero, and are not included in the header. the location of the first osd specification block of a field is defined by the vid_obp or vid_otp registers in units of 256 bytes. this means the full address of the first block must be a multiple of 64. field size bits meaning ref. m 1 63 palette mode. table 78 q162 e161 tc 1 60 0: select 14-bit color mode 1: select 24-bit color mode table 79 p 1 59 0: a new palette follows the header. 1: the palette is the same as the previous region. table 77 aa 1 58 select anti-aliasing. anti-aliasing can only be used with 24-bit color. section 18.4.5 s 1 57 osd region not included in cvbs output in dual output mode. below y_top 9 56:48 position of the top of the osd region. section 18.4.4. mixweight 4 47:44 mixing weight 2 with planes behind when anti-aliasing is dis- abled. when anti-aliasing is enabled, write 0. section 18.4.9 osdp[6:4] 3 43:41 pointer to the next region specification. below y_bottom 9 40:32 position of the bottom of the osd region. section 18.4.4. osdp[12:7] 6 31:26 pointer to the next region specification. below x_left 10 25:16 position of the left of the osd region. section 18.4.4. osdp[18:13] 6 15:10 pointer to the next region specification. below x_right 10 9:0 position of the right of the osd region. section 18.4.4. table 85 osd block header format m q e tc p aa s y_top mixweight osdp[6:4] y_bottom osdp[12:7] x_left osdp[18:13] x_right table 86 osd region specification header
c o n f i d e n t i a l 18 display planes STI5518 178/294 7170179 d the bit s in table 87 on page 178 controls the presence of the osd on a region basis for the 4:2:2 path to the digital encoder, from which yc and cvbs signals are generated. if this bit is 1, the osd region will not be present; if it is set to 0, the osd region will be present provided the osd is included in the 4:2:2 output, as defined by vid_out . this is to allow selective recording of osd regions. this bit does not affect the 4:4:4 path to the digital encoder from which the rgb and ycbcr signals are generated. 18.4.8 osd specification block examples this section shows the format for some complete specification blocks. the table below shows a specification using 2 bits per pixel in the bit-map with 1 pel resolution and 14-bit color. only the first 8 pixels of the bit-map are shown. the palette occupies one 64-bit word, and the bit-map occupies one 64-bit word for every 32 pixels. bits within a 16-bit quarter-word description 15 14 13 12 11 10 98 76543210 m=0 q=0 e=0 tc=0 p=0 a=0 s y_top word 0 mixweight osdp[6:4] y_bottom osdp[12:7] x_left osdp[18:13] x_right palette0 y 0 t0 palette0 cb palette0 cr word 1 palette1 y 0 t1 palette1 cb palette1 cr palette2 y 0 t2 palette2 cb palette2 cr palette3 y 0 t3 palette3 cb palette3 cr bit-map for 8 osd pixels bit-map word table 87 2 bits per pixel, 14-bit color osd region specification
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 179/294 the table below shows a specification using 4 bits per pixel in the bit-map with 2 pel resolution and 14-bit color. only the first 4 pixels of the bit-map are shown. each entry in the bit-map uses 4 bits, but defines two display pels of the same color. the palette occupies four 64-bit words, and the bit-map occupies one 64-bit word for every 16 bit-map pixels. bits within a 16-bit quarter-word description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m=1 q=1 e=0 tc=0 p=0 aa=0 s y_top word 0 mixweight osdp[6:4] y_bottom osdp[12:7] x_left osdp[18:13] x_right palette0 y 0 t0 palette0 cb palette0 cr word 1 palette1 y 0 t1 palette1 cb palette1 cr palette2 y 0 t2 palette2 cb palette2 cr palette3 y 0 t3 palette3 cb palette3 cr palette4 y 0 t4 palette4 cb palette4 cr word 3 palette5 y 0 t5 palette5 cb palette5 cr palette6 y 0 t6 palette6 cb palette6 cr palette7 y 0 t7 palette7 cb palette7 cr palette8 y 0 t8 palette8 cb palette8 cr word 4 palette9 y 0 t9 palette9 cb palette9 cr palette10 y 0 t10 palette10 cb palette10 cr palette11 y 0 t11 palette11 cb palette11 cr palette12 y 0 t12 palette12 cb palette12 cr word 5 palette13 y 0 t13 palette13 cb palette13 cr palette14 y 0 t14 palette14 cb palette14 cr palette15 y 0 t15 palette15 cb palette15 cr bit-map for 4 osd pixels bit-map word table 88 4 bits per pixel, 2-pel resolution 14-bit color osd region specification
c o n f i d e n t i a l 18 display planes STI5518 180/294 7170179 d the table below shows a specification using 8 bits per pixel in the bit-map with full resolution and 14-bit color. only the first 2 pixels of the bit-map are shown. each pixel in the bit-map uses 8 bits. the palette occupies 64 64-bit words (i.e. 512 bytes), and the bit-map occupies one 64-bit word for every 8 bit-map pixels. the table below shows a specification using 2 bits per pixel in the bit-map with full resolution and 24-bit color, without anti-aliasing. only the first 8 pixels of the bit-map are shown. each entry in the bit-map uses 2 bits. the palette occupies two 64-bit words, and the bit-map occupies one 64-bit word for every 32 bit-map pixels. the palette for 4-bit and 8-bit colors would be similar, but with 16 or 256 color lines in the palette instead of 4. bits within a 16-bit quarter-word description 15 14 13 12 11 10 98 76543210 m=0 q=0 e=1 tc=0 p=0 aa=0 s y_top word 0 mixweight osdp[6:4] y_bottom osdp[12:7] x_left osdp[18:13] x_right palette0 y 0 t0 palette0 cb palette0 cr word 1 palette1 y 0 t1 palette1 cb palette1 cr palette2 y 0 t2 palette2 cb palette2 cr palette3 y 0 t3 palette3 cb palette3 cr palette4 y 0 t4 palette4 cb palette4 cr word 2 ... ... ... ... palette252 y 0 t12 palette252 cb palette252 cr word 64 palette253 y 0 t13 palette253 cb palette253 cr palette254 y 0 t14 palette254 cb palette254 cr palette255 y 0 t15 palette255 cb palette255 cr bit-map for 2 osd pixels with 8 bits per pel or 8 bits per 2 pel bit-map word table 89 8 bits per pixel, 14-bit color osd region specification bits within a 16-bit quarter-word description 15 14 13 12 11 10 98 76543210 m=0 q=0 e=0 tc=1 p=0 aa=0 s y_top word 0 mixweight osdp[6:4] y_bottom osdp[12:7] x_left osdp[18:13] x_right 0 (reserved) t0 palette0 y word 1 palette0 cb palette0 cr 0 (reserved) t1 palette1 y palette1 cb palette1 cr 0 (reserved) t2 palette2 y word 2 palette2 cb palette2 cr 0 (reserved) t3 palette3 y palette3 cb palette3 cr bit-map for 8 osd pixels bit-map word table 90 2 bits per pixel 24-bit color without anti-aliasing osd region specification
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 181/294 ta b le 9 1 shows a specification using 2 bits per pixel in the bit-map with full resolution and 24-bit color with anti-aliasing. only the first 8 pixels of the bit-map are shown. each entry in the bit-map uses 2 bits. the palette and bit-map occupy the same memory as without anti-aliasing. the palette for 4-bit and 8-bit colors would be similar, but with 16 or 256 color lines in the palette instead of 4. 18.4.9 mixing osd with video the mixing function allows each osd pixel to be blended with the corresponding pixel generated by the planes behind the osd. this is shown as 2 in figure 117 and figure 118 . the mix weight is a programmable parameter and can be set for each osd region, or for each color when anti-aliasing is enabled. when anti-aliasing is disabled, the mix weight is set for each region in the region header. the mix weight is a 4-bit number allowing mixing ratios from 0 to 1 with a resolution of 1/15. the resulting pixel can be completely transparent (weighting of 0/15) or can completely cover the video (15/15). each individual color in the palette can be specified to be used with or without mixing by setting the transparency (t) bit of the palette. a t bit equal to 0 means no mixing for the particular color, and a t of 1 means that mixing should be used. when anti-aliasing is enabled, a mix weight is defined for each color in each region in the lut. the mix weight is a 6- bit number allowing mixing ratios from 0 to 1 with a resolution of 1/63. the resulting pixel can be completely transparent (weighting of 0/63) or can completely cover the video (63/63). palette color zero can also be set to be transparent by setting the y, cb and cr values to zero. only palette color zero can be used in this way. 18.4.10 anti-flicker and anti-flutter filters flicker and flutter effects are visual problems due to interlaced television displays. flutter effects can occur if the same osd image is displayed in both fields within one frame. anti-flicker and anti-flutter filtering are provided as part of the display unit. bits within a 16-bit quarter-word description 15 14 13 12 11 10 9876543210 m=0 q=0 e=0 tc=1 p=0 aa=1 s y_top word 0 0 (reserved) osdp[6:4] y_bottom osdp[12:7] x_left osdp[18:13] x_right 0 mixweight0 palette0 y word 1 palette0 cb palette0 cr 0 mixweight1 palette1 y palette1 cb palette1 cr 0 mixweight2 palette2 y word 2 palette2 cb palette2 cr 0 mixweight3 palette3 y palette3 cb palette3 cr bit-map for 8 osd pixels bit-map word table 91 2 bits per pixel 24-bit color with anti-aliasing osd region specification
c o n f i d e n t i a l 18 display planes STI5518 182/294 7170179 d at every vsync pulse the values in the register osd_cfg are taken in account. the table below shows the register configurations for anti-flitter/ anti-flutter filtering. for flicker or flutter filtering the osd boundary weight can be specified in the register osd_bdw . this weight will be taken into account at osd top and bottom borders in filter modes. the anti-flicker filter can be described by the following expressions, where t is a top-field pixel, b is a bottom field pixel and n is the line number: the osd boundary weight register (osd_bdw) represents the value of mix_weight at the horizontal border of an osd region or at a horizontal border of a transparent region within an osd region. the osd_bdw value can be used if flicker problems occur at osd-video borders. the anti-flutter filter can be described by the following expression, where t is a top-field pixel, b is a bottom field pixel and n is the line number: 18.4.11 osd active signal the osd active signal can be used in two modes. the mode is controlled using osd_act.oam . in the first mode the osd active signal is configured as an output. in this mode the osd active signal denotes when an active osd pixel (non transparent) is on the yc output bus, as in table 93 . the signal, in this mode, has a programmable delay controlled by osd_act.oad . this delay can be set such that the osd active signal is set as much as two clocks before or 1 to 64 clocks after the actual pixel. osd_cfg.nor osd_cfg.fil filtering 0 0 or 1 none (normal mode) 1 0 anti-flicker filter applied 1 1 anti-flutter filter applied table 92 register configurations for anti-flitter/ anti-flutter filtering figure 115 osd active timing when osd_act.oam = 1 t bn 1 ? [] 2t n [] bn [] ++ () 4 ------------------------------------------------------------------- - = b tn [] 2b n [] tn 1 + [] ++ () 4 ------------------------------------------------------------------- - = ttn [] = b tn [] tn 1 + [] + () 2 --------------------------------------------- = pixclk yc[7:0] with vid_dcf.pxd = 0 yc[7:0] with vid_dcf.pxd = 1 osd active signal (input) osd active signal delay 32 3 1 2 0 1 0 enable osd pixels enable osd pixels y cr y cb y cr y cb
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 183/294 in the second mode of operation, the osd active signal is configured as an input and is used to disable the osd. when the signal goes high, the osd will be placed on the yc bus if the osd is enabled. when this signal is low then no osd will be placed on the bus even if osd is enabled. the programmable delay is used in the same way as for the input signal. 18.5 sub-picture or cursor plane the sub-picture or cursor plane displays the output from the sub-picture decoder, described in sub-picture decoder on page 150 . the sub-picture can be either in front of or behind the osd, depending on whether the bit vid_out.spo is 1 or 0 respectively. the sub-picture decoder can also be used as a hardware cursor unit. the sub-picture should be configured to be in front of the osd. a cursor can be defined using an optionally compressed (run-length encoded) bitmap stored in external sdram. the bitmap can be any size up to a full screen. per-pixel alpha-blending factors can be defined for each cursor to provide anti-aliasing with the background. the cursor is then moved around using register writes into x and y coordinate registers. 18.6 mixing display planes the blending of the elements of the final picture is performed by a mixing unit, which is shown in ta b le 9 4 and figure 117 . the mixing of the display planes is controlled by five mix weights, 1 to 5. osd active mode osd active signal meaning 0 0 signal is an output. video pixels only on display bus. 0 1 signal is an output. osd pixels on the display bus. 1 0 signal is an input. disable the osd output. 1 1 signal is an input. enable osd output if available. table 93 osd active signal operation figure 116 osd active timing when osd_act.oam = 0 pixclk yc[7:0] osd active signal (output) osd active signal delay 0123 osd pixels y cr y cb y cr y cb
c o n f i d e n t i a l 18 display planes STI5518 184/294 7170179 d the mix weights value ( 1) controls the mixing of the the background color plane and the video plane. it is an 8-bit values held in the vid_mwv register, as shown in table 94 . the two back planes are generated and mixed in 4:2:2 format and then converted to 4:4:4 for mixing with the sub-picture and osd. the resultant of mixing the back three planes can be blended in turn with the sub-picture and osd. the mixing formula is: display=( 1- ) x source1 + x source2. the mixing order depends on whether the sub-picture is in front of or behind the osd. the osd mix weight is 2 and is defined in the osd palette. if anti-aliasing is disabled, then the mix weight is a 4-bit value, defined for each osd region, and mixing can be enabled or disabled for each color. if anti-aliasing is enabled, then the mix weight is a 6-bit value defined for each color. blending the osd is described in section 18.4.9. the sub-picture mix weight is 3, which is a 4-bit value defined per pixel type. these values can be controlled by the sub-picture bit stream except in the highlight area which is controlled by spd_hcn. factor register mixed planes plane displayed when mix weight is 0 plane displayed when mix weight is 0xff 1 vid_mwv background color and mpeg video mpeg video background color table 94 control of mixing factor 1 figure 117 mixing with the sub-picture in front background color video plane osd sub- picture color palette (lut) 1 chroma filter 2 3 cvbs yc yuv rgb yuv to rgb 4:2:2 4:2:2 4:4:4 4:4:4 2 value for whole region (16 levels) or blend per lut entry (64 levels) 4:4:4 user selectable and by region osd bit chroma deci- mate full 4:4:4 graphics format supported for rgb/yuv outputs 1 value 4:4:4 4:4:4 sp mix (16 levels) 4:2:2 selection of video overlays for 4:2:2 output pal / ntsc/ secam encoder
c o n f i d e n t i a l STI5518 18 display planes 7170179 d 185/294 18.6.1 4:2:2 output control the 4:2:2 output is used by the denc to generate cvbs and yc output, and is generally used for recording by vcr. the osd and sub-picture can be omitted from this output, as controlled by the register vid_out and by the s bits in the osd region headers. the combined actions of these fields depend on whether the osd is behind or in front of the sub-picture. the 4:4:4 output is unaffected. vid_out.lay defines the number of planes in front of the video which are initially included. vid_out.nos turns on or off the osd, as shown in table 95 . if vid_out.nos=0 (osd present) then the s bit in an osd region header can alternatively be used to turn off that osd region. when the osd and sub-picture planes are present,vid_out.spo defines which plane is in front. the comibation of bit functions is given in the table below. figure 118 mixing with the osd in front lay nos sub-picture in front (sp0=1) osd in front (sp0=0) 00-01 any video only video only 10 0 video + osd video + sub-picture 1 video only video + sub-picture 11 0 video + osd + sub-picture video + sub-picture + osd 1 video + sub-picture video + sub-picture table 95 encoding of lay and nos fields of vid_out background color video plane sub- picture color palette (lut) 1 chroma filter 3 2 cvbs yc yuv rgb yuv to rgb 4:2:2 4:4:4 4:4:4 2 value for whole region (16 levels) sp mix or blend per lut entry (64 levels) 4:4:4 user selectable and by region osd bit selection of video overlays for 4:2:2 output chroma deci- mate full 4:4:4 graphics format supported for rgb/yuv outputs 1 value 4:4:4 4:4:4 osd (16 levels) 4:2:2 4:2:2 pa l/ ntsc/ secam encoder
c o n f i d e n t i a l 19 sdram block move STI5518 186/294 7170179 d 19 sdram block move this sdram block move module, copies blocks of data from one byte address within the sdram to another. the source address, destination address and the number of bytes to be transferred are specified by the sdram block move registers listed in table 96 .the registers are all serial read/write registers in the peripheral address space. to perform a sdram block move from one sdram memory buffer to another, the block move size, destination address and read address must be set by the registers listed in the table below. registers usd_bms and usd_bwp must be written before usd_brp, as t he third write to usd_brp initiates the block move. while a block move is in progress, all other accesses to the sdram are disabled. the progress of the block move can be monitored using register bit vid_sta.bmi. this bit is set while a block move is in progress, and reset when the block move engine is idle. when the block move is finished, an interrupt is generated if the mask bit vid_itm.bmi is set. register bits name usd_bms 15:0 block move size usd_bwp 19:0 memory write pointer usd_brp 19:0 memory read pointer table 96 sdram block move registers
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 187/294 20 digital encoder 20.1 introduction this the final stage of the video pipeline of the device is a high performance pal/secam/ntsc digital encoder referred to as the denc. the denc converts a 4:2:2 digital video stream into a standard analog baseband pal/ secam/ntsc signal and into rgb and yuv analog components. the denc can perform closed-captions, cgms, wss, teletext and vps encoding and allows macrovision tm 7.01/ 6.1 copy protection. six analog output pins are available, on which it is possible to output either (s-vhs(y/c) + cvbs + rgb) or (s-vhs(y/c)+ cvbs + v + y + u) or (y1 + c1 + cvbs1 + c2 + y2 + cvbs2). the encoder can operate in master mode or in one of several slave modes, where it locks onto incoming sync signals. an auto-test mode is also provided. the main functions are controlled using an 8-bit register interface with the cpu. the registers are described in the STI5518 register manual . 20.2 video timing the burst sequences are internally generated, subcarrier generation being performed numerically with ckref as reference. 4-frame bursts are generated for pal or 2-frame bursts for ntsc. rise and fall times of synchronization tips and burst envelope are internally controlled according to the relevant itu-r and smpte recommendations. the 6- frame subcarrier phase sequence is generated in secam (see subcarrier insertion (secam) on page 200 ). figure 121 , figure 122 and figure 123 depict typical vbi (vertical blanking interval) waveforms. it is possible to encode incoming ycrcb data on those lines of the vbi that do not bear line sync pulses or pre/post- equalization pulses (see figures 121, 122 and 123). this mode of operation is referred to as partial blanking and is the default set-up. it allows the encoded waveform to keep any vbi data present in digitized form in the incoming ycrcb stream (e.g. supplementary closed-caption lines or starsight data, etc.). in secam mode, only y data are encoded, cr and cb are ignored. alternatively, the complete vbi may be fully blanked , so no incoming ycrcb data is encoded on these lines. full or partial blanking is set by register bit den_cfg1.blkli. for 525/60 systems, with the smpte line numbering convention: complete vbi consists of lines 1 to 19 and the second half of lines 263 to 282; partial vbi consists of lines 1 to 9 and the second half of lines 263 to 272; line 282 is either fully blanked or fully active. for 625/50 systems, with the ccir line numbering convention: complete vbi consists of the second half of lines 623 to 22 and lines 311 to 335; partial vbi consists of the second half of lines 623 to 5 and lines 311 to 318; line 23 is always fully active. in an itu-r656-compliant digital tv line, the active portion of the digital line is the portion included between the sav (start of active video) and eav (end of active video) words. however, this digital active line starts somewhat earlier and may end slightly later than the active line usually defined by analog standards. the denc allows two approaches: encodes the full digital line (720 pixels / 1440 clock cycles). in this case, the output waveform will reflect the full ycrcb stream included between sav and eav.
c o n f i d e n t i a l 20 digital encoder STI5518 188/294 7170179 d drops some ycrcb samples at the extremities of the digital line so that the encoded analog line fits within the analog itu-r/smpte specifications. in all cases, the transitions between horizontal blanking and active video are shaped to avoid too steep edges within the active video. figure 124 gives typical timings concerning the horizontal blanking interval and the active video interval. note the burst envelope shown here indicates the location from which the first subcarrier positive zero crossing is sought (with respect to the 0 h reference). the normal burst always starts with such a positive zero crossing. figure 119 input data format (itu-r656 /d1 4:2:2) digital active line 1440t 1716t ntsc, pal m square pixel 525 / 60 system square pixel 625 / 50 system 4t ese a v a v a v 4t 128t 137t 146t (pal m) digital active line 1440t 1728t 128t digital active line 1280t 1560t 115t 131t digital active line 1536t 1888t 139t 169t 0h pal b, g, h, i, n secam t = clock period pal, ntsc and secam: 37.037 ns square pixel pal: 33.898 ns square pixel ntsc: 40.75 ns 151t (145t in secam)
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 189/294 note 1. these diagrams are valid with contents of ? delay ? and ? synchro-delay ? register fields equal to the default values. 2. if on-the-fly format changing is required, clock switching must be synchronized onto the start of frame as shown in the above waveform. internally, sqpix bit update is taken into account on the beginning of a new frame. figure 120 square pixel mode switch master mode slave mode by oddeven and hsync slave mode by oddeven only oddeven (output) ckref hsync (output) oddeven (input) ckref hsync (input) oddeven (input) ckref field2 field1 field1 field1 clock period change if square pixel mode switch update of sqpix bit clock period change if square pixel mode switch update of sqpix bit clock period change if square pixel mode switch update of sqpix bit
c o n f i d e n t i a l 20 digital encoder STI5518 190/294 7170179 d figure 121 pal-bdghi, pal-n typical vbi waveform, interlaced mode (itu-r625 line numbering) figure 122 ntsc-m typical vbi waveforms, interlaced mode (smpte-525 line numbering) a 311 312 313 314 315 316 317 318 317 336 308 309 310 ab 624 625 1 2 3 4 5 6 7 8 621 622 623 iii i ii iii iv ii c 0 v : i, ii, iii, iv : a : b : c : frame synchronization reference 1 st and 5 th , 2 nd and 6 th , 3 rd and 7 th , 4 th and 8 th fields burst phase : nominal value +135 burst phase : nominal value -135 burst suppression internal 308 309 310 311 312 313 314 315 316 317 318 319 320 ab 0 v iv a 624 625 1 2 3 4 5 6 7 23 621 622 623 i partial vbi1 full vbi1 partial vbi2 full vbi2 22 335 1 full vbi1 2 3 partial vbi1 4 5 6 7 8 9 10 18 19 h 0.5h h h 282 273 272 271 270 269 268 267 266 265 264 263 262 h h 0.5h full vbi2 vbi3 1 2 3 4 5 6 7 8 9 10 18 19 525 282 273 272 271 270 269 268 267 266 265 264 263 vbi4 partial vbi2
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 191/294 figure 123 pal-m typical vbi waveforms, interlaced mode (itu-r/ccir-525 line numbering) figure 124 horizontal blanking interval and active video timings ntsc-m pal-bdghi pal-n pal-m secam a 1 5.38 s (even lines) 5.52 s (odd lines) 5.54 s (a-type) 5.66 s (b-type) 5.54 s (a-type) 5.66 s (b-type) 5.73 s (a-type) 5.87 s (b-type) 5.60 s b1 1.56 s1.3 s1.3 s 1.56 s1.0 s b2 1.56 s 1.52 s 1.52 s 1.56 s 1.52 s c1 8.8 s9.6 s9.6 s8.8 s9.9 s table 97 typical timing values for figure 124 f' 519 f 520 f' 521 f 522 523 524 525 1 2 3 4 5 6 7 8 9 ab ab ab 261 262 263 264 265 266 267 268 269 270 271 280 523 524 525 1 2 3 4 5 6 7 8 9 f 519 f' 520 f 521 522 f 257 f' 258 f 259 260 ab 261 262 263 264 265 266 267 268 269 270 271 272 f' 257 f 258 259 260 0 v iv i ii iii iv iii ii i c 0 v : i, ii, iii, iv : a : b : c : frame synchronization reference 1 st and 5 th , 2 nd and 6 th , 3 rd and 7 th , 4 th and 8 th fields burst phase : nominal value +135 burst phase : nominal value -135 burst suppression internal partial vbi1 full vbi1 16 17 partial vbi2 full vbi2 279 0h active video horizontal blanking interval a b1 (bit aline = 0) c1 (bit aline = 0) c2 (bit aline = 1) d full digital line encoding ? analog ? line encoding (720 pixels - 1440 t) b2 (bit aline = 1)
c o n f i d e n t i a l 20 digital encoder STI5518 192/294 7170179 d 20.3 reset procedure a hardware reset sets the denc in hsync+oddeven (line-locked) slave mode, for ntsc-m, interlaced itu-r601 encoding closed-captioning, wss, vps, teletext and cgms encoding are all disabled. the configuration can then be customized by writing into the appropriate registers. a few registers are never reset, their contents are unknown until the first loading (see the STI5518 register manual). it is also possible to perform a software reset by setting the 7th bit in the den_cfg6 register. the device responds in a similar way as after a hardware reset except that the configuration registers and a few other registers are not altered. 20.4 master mode in this mode, the encoder supplies hsync and oddev sync signals (with independently programmable polarities) to drive other blocks. refer to the following figures for timings and waveforms. the encoder starts encoding and counting clock cycles as soon as the master mode has been loaded into the control register den_cfg0. configuration bits syncout_ad[1:0] (register den_cfg4) shift the relative position of the sync signals by up to 3 clock cycles to cope with any ycrcb phasing. note 1. when oddev is a sync input, only one edge ( ? the active edge ? ) of the incoming oddev is taken into account for synchronization. the ? non-active ? edge (2nd edge on this drawing) is not critical and its position may differ by h/2 from the location shown. note 2. the hsync pulse width indicated is valid when the denc supplies hsync. in those slave modes where it receives hsync, only the edge defined as active is relevant, and the width of the hsync pulse it receives is not critical. c2 9.41 s 10.48 s 10.48 s 9.41 s 10.48 s d 9 cycles of 3.58 mhz 10 cycles of 4.43 mhz 9 cycles of 3.58 mhz 9 cycles of 3.58 mhz - 1. these are typical values, actual values will dep end of the static offset programmed for subcarrier generation. figure 125 oddeven, vsync and hsync waveforms ntsc-m pal-bdghi pal-n pal-m secam table 97 typical timing values for figure 124 active edge (programmable polarity) active edge (programmable polarity) active edge (programmable polarity) 128 t ckref = 4.74 s oddeven (see note 1) vsync hsync (see note 2) line numbers : smpte-525 ccir-625 4 1 5 2 6 3 266 313 267 314 268 315 269 316
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 193/294 note this figure is valid for bits ? syncout_ad[1:0] ? = default 20.5 slave modes 20.5.1 introduction the following slave modes are available: oddeven(vsync) + hsync based (line-based sync), oddeven(vsync)-only based (frame-based sync), sync-in-data based (line locked or frame locked). oddeven refers to an odd/even field flag, also known as bottomtop. hsync is a line sync signal and vsync is a vertical sync signal. their waveforms are depicted in figure 127 . the polarities of hsync and oddeven(vsync) are independently programmable in all slave modes. in all slave modes, odd even(vsync) and/or hsync signals must be related to ckref, the principal denc clock. in other words, there is no genlocking performed by the denc. 20.5.2 line-based synchronization oddeven+hsync based synchronization synchronization is performed on a line-by-line basis by locking onto incoming oddeven and hsync signals. refer to figure 127 for waveforms and timings. the polarities of the active edges of hsync and odd even are programmable and independent. the first active edge of odd even initializes the internal line c ounter but encoding of the first line does not start until an hsync active edge is detected (at the earliest, an hsync transition may be at the same time as oddeven). at that point, the internal sample counter is initialized and encoding of the first line starts. then, encoding of each subsequent line is individually triggered by hsync active edges. the phase relationship between hsync and the incoming ycrcb data is normally such that the first clock rising edge following the hsync active edge samples cb (i.e. a blue chroma sample within the ycrcb stream). it is however possible to internally delay the incoming sync signals (hsync+oddeven) by up to 3 clock cycles to cope with different data/sync phases, using configuration bits syncin_ad in den_cfg4. the denc is thus fully slaved to the hsync signal, which means that lines may contain more or less samples than usual. if the digital line is shorter than its nominal value, the sample counter is re-initialized when the ? early ? hsync arrives and all internal synchronization signals are re-initialized. figure 126 master mode sync signals hsync (out) oddeven (out) ckref ycrcb cb ycry' active edge (programmable polarity) active edge (programmable polarity) 1t ckref duration of hsync pulse : 128 t ckref cr y'
c o n f i d e n t i a l 20 digital encoder STI5518 194/294 7170179 d if the digital line is longer than its nominal value, the sample counter is stopped when it reaches its nominal end-of- line value and waits for the ? late ? hsync before re-initializing. note this figure is valid for bits syncin_ad[1:0] = default hsync+vsync based synchronization synchronization is performed on a line-by-line basis by locking onto incoming vsync and hsync signals. refer to figure 128 for waveforms and timings. the polarities of hsync and vsync are programmable and independent. the incoming vsync signal is immediately transformed into a waveform identical to the odd/even waveform of an oddeven signal, therefore, the behavior with this synchronization is identical to that described above for oddeven+hsync based synchronization. again, the phase relationship between hsync and the incoming ycrcb data is normally such that the first clock rising edge following the hsync active edge samples ? cb ? (i.e. a 'blue' chroma sample within the ycrcb stream). it is however possible to internally delay the incoming sync signals (hsync+vsync) by up to 3 clock cycles to cope with different data/sync phasing, using configuration bits syncin_ad (den_cfg4). 20.5.3 frame-based synchronization oddeven-only based synchronization synchronization is performed on a frame-by-frame basis by locking onto an incoming oddeven signal. a line sync signal is derived internally and is also issued to the outside as hsync. refer to figure 129 for waveforms and timings. the phase relationship between oddeven and the incoming ycrcb data is normally such that the first clock rising edge following the odd even active edge samples ? cb ? (i.e. a ? blue ? chroma sample within the ycrcb stream). it is figure 127 hsync + oddeven based slave mode sync signals cb y cr y cb ckref oddeven (in) ycrcb hsync (in) active edge (programmable polarity) active edge (programmable polarity)
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 195/294 however possible to internally delay the incoming oddeven signal by up to 3 clock cycles to cope with different data/ sync phasing, using configuration bits syncin_ad in den_cfg4. note 1. this figure is valid for bits ? syncin_ad[1:0] ? = default. 2. the active edges of hsync and vsync should normally be simultaneous. it is permissible that hsync transitions before vsync, but vsync must not transition before hsync. note this figure is valid for bits syncin_ad[1:0] = default the first active edge of oddeven triggers generation of the analog sync signals and encoding of the incoming video data. frames being supposed to be of constant duration, the next oddeven active transition is expected at a precise time after the last oddeven detected. so, once an active oddeven edge has been detected, checks that the following oddeven are present at the expected instants are performed. encoding and analog sync generation carry on unless three successive fails of these checks occur. in that case, three behaviors are possible, according to the configuration programmed in registers den_cfg1-2: if freerun is enabled, the denc carries on outputting the digital line sync hsync and generating analog video just as though the expected oddeven edge had been present. however, it will re-synchronize onto the next oddeven active edge detected, whatever its location. if freerun is disabled but bit syncok is set in the configuration registers, the denc sets the active portion of the tv line to black level but carries on outputting the analog sync tips (on ys and c vbs) and the digital line sync signal hsync. when programmed, macrovision tm pseudo-sync pulses and agc pulses are also present in the analog sync waveform. figure 128 hsync + vsync based slave mode sync signals figure 129 oddeven based slave mode sync signals cb y cr y cb ckref vsync (in) ycrcb hsync (in) active edge (programmable polarity) active edge (programmable polarity) cb y cr y cb ckref oddeven (in) ycrcb
c o n f i d e n t i a l 20 digital encoder STI5518 196/294 7170179 d if freerun is disabled and bit syncok is not set, all analog video is at black level and neither analog sync tips nor digital line sync are output. this mode is a frame-based sync mode, as opposed to a field-based sync mode. this means that only one type of edge (rising or falling, according to programming) is of interest to the denc; the other one is ignored. vsync-only based synchronization synchronization is performed on a frame-by-frame basis by locking onto an incoming vsync signal. an auxiliary line sync signal hsync must also be fed to the denc, which uses it to reconstruct from vsync and hsync information an internal odd/ even waveform identical to that of an oddev signal. therefore, the behavior with this synchronization is identical to that described above for oddev-only based synchronization (except that nothing is output on hsync pin since it is an input port in this mode). note that hsync is an input but has no other use than allowing the denc to decide whether an incoming vsync pulse flags an odd or an even field. in other words, the denc does not lock onto hsync in this mode since this is not a line-locked mode. the phase relationship between vsync and the incoming ycrcb data is normally such that the first clock rising edge following the vsync active edge samples ? cb ? (i.e. a 'blue' chroma sample within the ycrcb stream). it is however possible to internally delay the incoming sync signals (vsync+hsync) by up to 3 clock cycles to cope with different data/sync phasing, using configuration bits syncin_ad (den_cfg4). 20.5.4 sync-in-data based synchronization ? end-of-frame ? word-based synchronization synchronization is performed by extracting the 1-to-0 transitions of the ? f ? flag (end-of-frame) from the ? eav ? (end-of- active video) sequence embedded within itu-r656 / d1 compliant digital video streams. both a frame sync signal and a line sync signal are derived and are made available externally as oddev and hsync. refer to figure 130 for waveforms and timings. the first successful detection of the ? f ? flag triggers generation of the analog sync signals and encoding of the incoming video data. frames being supposed to be of constant duration, the next eav word containing the ? f ? flag is expected at a precise time after the latest detection. so, once an active ? f ? flag has been detected, checks that the following flags are present within the incoming video stream at the expected times are performed. encoding and analog sync generation carry on unless there are three successive fails of these checks. then, depending on the programmed configuration, one of the following three events occurs: figure 130 data (eav) based slave mode sync signals hsync duration = 128 tclkref ckref oddev ycrcb hsync 00 b6 cb y eav 00 ff 46tclkref 1tclkref (out) (out)
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 197/294 if free-run is enabled, the denc carries on generating the digital frame and line syncs (oddev and hsync) and generating analog video just as though the expected f flag had been present. however, it will re-synchronize onto the next f flag detected within the incoming itu-r656/ d1 video stream. if free-run is disabled but the bit syncok is set in the configuration registers, the denc sets the active portion of the tv line to black level but carries on outputting the analog sync tips (on ys and cvbs) and the digital frame and line sync signals oddev and hsync. (when programmed, macrovisiontm pseudo-sync pulses and agc pulses are also present in the analog sync waveform). if free-run is disabled and the bit syncok is not set, all analog video is at black level and neither analog sync tips nor digital frame/line sync are output. the sav and eav words are hamming-decoded. after detection of two successive errors, a bit is set in the status register to inform the micro-controller of the poor transmission quality. ? end-of-line ? word-based synchronization synchronization is performed by extracting the f and ? h ? flags from the sav (start of active video) and eav (end of active video) words embedded within itu-r656/d1 compliant digital video streams. a line sync signal and a frame sync signal are derived from these flags and are issued to the outside on the hsync and odd even/vsync pins in output mode. these signals are also used by the denc, which treats them as incoming oddeven and hsync signals in hsync+odd even based synchronization. auto-test mode an auto-test mode is available, which causes the denc to produce a color bar pattern, in the appropriate standard, independently from the video input. the auto-test mode is started by setting to 7 the 3-bit field sync in the register den_cfg0. as this mode sets the denc in master mode, vsync/oddeven and hsync signals are in output mode. in table below, the decimal values of y, cr and cb are shown corresponding to the auto-test color bar. ycrcb black 16 128 128 blue 36 116 212 red 64 212 100 magenta 84 200 184 green 112 56 72 cyan 136 44 156 yellow 160 140 44 white 236 128 128 table 98 auto-test colors
c o n f i d e n t i a l 20 digital encoder STI5518 198/294 7170179 d the corresponding decimal output values just before the dacs are shown graphically in figure 132 and figure 133 . both figures show the static values corresponding to the input values in table 98 . 20.6 input demultiplexor the incoming ycrcb data, as well as y4 and crcb in 4:4:4 mode, is demultiplexed into a ? blue-difference ? chroma information stream, a ? red-difference ? chroma information stream and a luma information stream. incoming data bits are treated as blue, red or luma samples according to their relative position with respect to the sync signals in use and the contents of configuration bits syncin_ad (slave modes) or syncout_ad (master mode). brightness, saturation and contrast are then performed on demultiplexed data, refer to the register manual registers den_reg_69, den_reg_70 and den_reg_71. the itu-r601 recommendation defines the black luma level as y=16 and the maximum white luma level as y = 235. similarly, it defines 225 quantification levels for the color difference components (cr, cb), centered around 128. after figure 131 luminance output levels in auto-test for ntsc without set-up figure 132 luminance output levels in auto-test for pal (bghi) and secam sync level 240 16 white ye ll ow cyan green magenta red blue blank level black 240 black 800 608 546 486 414 362 290 sync level 256 16 white ye ll ow cyan green magenta red blue blank level black 256 black 816 624 562 502 430 378 306
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 199/294 the saturation, brightness and contrast stage, the incoming ycrcb samples can be saturated in the input multiplexer with the following rules: this avoids having to heavily saturate the composite video codes before digital-to-analog conversion in case erroneous or unrealistic ycrcb samples are input to the encoder (there may otherwise be overflow errors in the codes driving the dacs), and therefore avoids generating a distorted output waveform. however, in some applications, it may be desirable to let extreme ycrcb codes pass through the demultiplexor. this is controlled using bit maxdyn in register den_cfg6. in this case, only codes 0x00 and 0xff are overridden; if such codes are found in the active video samples, they are forced to 0x01 and 0xfe. in any case, the ycrcb codes are not overridden for eav/sav decoder. 20.7 subcarrier generation a direct digital frequency synthesizer (ddfs) generates the required color subcarrier frequency using a 24-bit phase accumulator. this oscillator feeds a quadrature modulator which modulates the base-band chrominance components. the subcarrier frequency is obtained from the following equation: where increment _word is a 24-bit value. hard-wired increment_word values are available for each standard and can be automatically selected. alternatively (according to bit selrst_inc in den_cfg5), the frequency can be fully customized by programming other values into a dedicated increment_word register, den_idfs. this allows, for instance, the encoding of ntsc-4.43 or pal-m-4.43. this is done with the following procedure: program the required increment in den_idfs. set bit selrst_inc to 1 in register den_cfg5. perform a software reset using register den_cfg6. this sets all bits in all denc registers except den_cfgn to their default value. alternatively, set den_cfg8 bits ph_rst_mode[1:0] to 01. then the frequency (and phase) update is done on the beginning of the next video line. warning: if a standard change occurs after the software reset, the increment value is automatically re-initialized with the hard wired or loaded value according to bit selrst the reset phase of the color subcarrier can also be software-controlled by register den_pdfs. the subcarrier phase can be periodically reset to its nominal value to compensate for any drift introduced by the finite accuracy of the calculations. in pal and ntsc subcarrier phase adjustment can be performed every line, every eight fields, every four fields, or every two fields (den_cfg2 bits valrst[1:0]). if secam is performed, the subcarrier phase is reset every line. for cr or cb samples: cr,cb > 240 => cr,cb saturated at 240 cr,cb < 16 => cr,cb saturated at 16 for y samples: y > 235 => y saturated at 235 y < 16 => y saturated at 16 fsc = ( increment_word / 2 24 ) x ckref
c o n f i d e n t i a l 20 digital encoder STI5518 200/294 7170179 d 20.8 burst insertion (pal and ntsc) the color reference burst is inserted so as to always start with a positive zero crossing of the subcarrier sine wave. the first and last half-cycles have a reduced amplitude so that the burst envelope starts and ends smoothly. the burst contains 9 or 10 sine cycles of 4.43361875 mhz or 3.579545 mhz (depending on the standard programmed in the register den_cfg0) as follows: the burst can be turned off (no burst insertion) by setting den_cfg2 configuration bit bursten to 0. burst insertion is performed by always starting the burst with a positive-going zero crossing. this guarantees a smooth start and end of burst with a maximum of undistorted burst cycles and can only be beneficial to chroma decoders. this avoids an uncontrolled initial burst phase, and guarantees a start on a positive-going zero crossing with the consequence that two burst start locations are visible over successive lines, according to the line parity. this is normal and explained below. in ntsc, the relation between subcarrier frequency and line length creates a 180 o subcarrier phase difference ( with respect to the horizontal sync ) from one line to the next according to the line parity. so if the burst always starts with the same phase (positive-going zero crossing), this means the burst will be inserted at time x or at time x+t ntsc /2 after the horizontal sync tip according to the line parity, where t ntsc is the duration of one cycle of the ntsc burst. with pal, a similar rationale holds, and again there will be two possible burst start locations. the subcarrier phase difference ( with respect to the horizontal sync ) from one line to the next in that case is either 0 or 180 o with the following series: a-a-b-b-a-a-...-etc. where a denotes ? a-type ? bursts and b denotes ? b-type ? bursts, a-type and b-type being 180 o out of phase with respect to the horizontal sync. so two locations are possible, one for a-type, the other for b-type. this assumes a periodic reset of the subcarrier is automatically performed (see bits valrst[1:0] in den_cfg2). otherwise, over several frames, the start of burst will drift within an interval of half a subcarrier ? s cycle. this is normal and means the burst is correctly locked to the colors encoded. the equivalent effect with a gated burst approach would be the following: the start location would be fixed but the phase with which the burst starts ( with respect to the horizontal sync ) would be drifting. 20.9 subcarrier insertion (secam) subcarrier frequency in secam mode depends on cr and cb values (frequency modulation). the color subcarrier frequency is 4,250,000 hz for cb=128 (on blue lines) and 4,406,249 hz for cr=128 (on red lines). frequency clipping values are 3,900,000 hz and 4,756,250 hz. ntsc-m 9 cycles of 3.579545 mhz pal-bdghi 10 cycles of 4.43361875 mhz pal-m 9 cycles of 3.579545 mhz pal-n 9 cycles of 3.579545 mhz
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 201/294 the insertion point of the non-modulated subcarrier is shown in the figure below. in odd fields the phase of subcarrier follows the sequence: 0, 0, , 0, 0, , 0, 0, , ... comparing to a sine wave starting at the same point - 5.6 s after horizontal synch pulse (inverted on one line out of every three and also at each frame). this sequence begins from line 1 or line 23 of the first field (see gen_secam bit of register den_cfg7). den_cfg7 bit inv_phi_secam allows the inversion of this sequence ( , , 0, , , 0,... instead of 0, 0, , 0, 0, ,...), in odd fields. in even fields the sequence of subcarrier is always inverted with respect to the odd field one. to enable secam mode, program a 1 in den_cfg7.7 (msb) and then perform a soft-reset or loading of den_cfg0. 20.10 luminance encoding the demultiplexed y samples are band-limited and interpolated at ckref clock rate. the resulting luminance signal is properly scaled before insertion of any closed-captions, cgms, vps, teletext or wss data and synchronization pulses. the interpolation filter compensates for the sin(x)/ x attenuation inherent in d/a conversion and greatly simplifies the output stage filter. see figures 134, 135 and 136 for characteristic curves. in addition, the luminance that is added to the chrominance to create the composite cvbs signal can be trap-filtered at 3.58 mhz (ntsc) or 4.43 mhz (pal). this supports applications oriented towards low-end tv sets which are subject to cross-color if the digital source has a wide luminance bandwidth (e.g. some dvd sources). note that the trap filter does not affect the s-vhs luminance output nor the rgb outputs. if secam is performed, enable the trap filter with 4.43 mhz cut-off frequency on the luma part of the cvbs signal (see den_cfg3 bits entrap and trap_4.43). figure 133 secam color bar pattern (blue line) 2.1 2.11 2.12 2.13 2.14 2.15 x 10 6 50 100 150 200 250 300 350 400 cvbs 5.6 s
c o n f i d e n t i a l 20 digital encoder STI5518 202/294 7170179 d a 7.5 ire pedestal can be programmed if needed with all standards (see registers den_cfg1 and den_cfg7). this allows in particular to encode argentinian and non-argentinian pal-n, or japanese ntsc (ntsc with no set-up). the luma processing as well as line and field timings in secam mode are identical to pal bdghi ones. figure 134 luma filtering including dac attenuation figure 135 luma filtering with 3.58 mhz trap, including dac attenuation figure 136 luma filtering with 4.43 mhz trap, including dac attenuation amplitude (db) 12345678910111213 frequency (mhz) -40 -35 -30 -25 -20 -15 -10 -5 0 amplitude (db) 12345678910111213 frequency (mhz) -40 -35 -30 -25 -20 -15 -10 -5 0 amplitude (db) 12345678910111213 frequency (mhz) -40 -35 -30 -25 -20 -15 -10 -5 0
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 203/294 20.11 chrominance encoding u, v (pal and ntsc) and dr, db (secam) chroma components are computed from demultiplexed cb, cr samples. before modulating the subcarrier, these are band-limited and interpolated at ckref clock rate. this processing eases the filtering following d/a conversion and allows more accurate encoding. a set of 4 different filters is available in pal and ntsc for chroma filtering to fit a wide variety of applications in the different standards and include filters recommended by itu-r 624-4 and smpte170-m. the available 3-db bandwidths are 1.1, 1.3, 1.6 or 1.9 mhz. see figures 139, 140, 141, 142 and 143 for the various frequency responses and register den_cfg1 for programming. the narrower bandwidths are useful against cross- luminance artifacts, the wider bandwidths allow higher chroma contents. in secam, 1.3 mhz low-pass and pre-emphasis filtering are performed on dr and db chroma components, before the frequency modulation, according to itu-r rec624-4. refer to figure 137 for frequency response of these filters. bell filtering is performed at the end of frequency modulation stage. peak to peak amplitude of modulated chrominance signal at the central frequency (4 279.7 khz) is 22,88% of the black- white interval (22.88 ire). refer to figure 138 for frequency response of bell filter with subcarrier frequencies and clipping values. figure 137 secam chroma filtering (pre-emphasis and 1.3 mhz low pass filtering) amplitude (db) 10 -1 10 0 frequency (mhz) -15 -10 -5 0 5 10
c o n f i d e n t i a l 20 digital encoder STI5518 204/294 7170179 d 20.12 composite video signal generation the composite video signal is created by adding the luminance (after trap filtering - optional in pal and ntsc, see register den_cfg3) and the chrominance components. a saturation function is included in the adder to avoid overflow errors should extreme luminance levels be modulated with highly saturated colors. this does not occur with natural colors but may be generated by computers or graphics engines. figure 138 secam high-frequency subcarrier pre-emphasis (bell filtering), including dac attenuation figure 139 various chroma filters available and rgb filter gain (db) frequency (mhz) 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 0 2 4 6 8 10 12 frequence (mhz) gain en db filtrage anti?cloche du secam (avec les dacs) amplitude (db) frequency (mhz) 0 0.5 1 1.5 2 2.5 3 3.5 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 rgb f -3 =1.9 f -3 =1.6 f -3 =1.3 f -3 =1.1
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 205/294 a ? color killing ? function is available, whereby the composite signal contains no chrominance, i.e. replicates the trap- filtered luminance. this function does not suppress the chrominance on the s/vhs outputs, but suppressing the s-vhs chrominance is possible using bit bkdac n in den_cfg5, where the chrominance signal is outputted on dac n . figure 140 1.1 mhz chroma filter figure 141 1.3 mhz chroma filter 02468101214 0 -5 -10 -15 -20 -25 -30 -35 -40 amplitude (db) frequency (mhz) 02468101214 0 -5 -10 -15 -20 -25 -30 -35 -40 amplitude (db) frequency (mhz)
c o n f i d e n t i a l 20 digital encoder STI5518 206/294 7170179 d 20.13 rgb and uv encoding after demultiplexing, the cr and cb samples feed a 4 times interpolation filter. the resulting base-band chroma signal has a 2.45 mhz bandwidth ( figure 144 ) and is combined with the filtered luma component to generate r,g,b or u,v samples at 27 mhz. figure 142 1.6 mhz chroma filter figure 143 1.9 mhz chroma filter 0 2 4 6 8 101214 0 -5 -10 -15 -20 -25 -30 -35 -40 amplitude (db) frequency (mhz) 02468101214 0 -5 -10 -15 -20 -25 -30 -35 -40 amplitude (db) frequency (mhz)
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 207/294 if y4 and crcb inputs are used, the filtering identical to luma filtering (see figure 134 ) is performed on all components (y4, cr and cb). in this case dac5 output data encoded from y4 input if yuv configuration is used (see den_cfg8 bits conf_out1 and conf_out0 ). 20.14 closed-captioning closed-captions (or data from an extended data service as defined by the closed-captions specification) can be encoded by the circuit. the closed-caption data is delivered to the circuit through the register interface. two dedicated pairs of bytes (two bytes per field), each pair preceded by a clock run-in and a start bit can be encoded and inserted on the luminance path on a selected tv line. the clock run-in and start code are generated by the denc. closed-caption data registers are double-buffered so that loading can be performed anytime, even during line 21/284 or any other selected line. user register den_ccf1 and den_ccf2 each contain the first and second byte to send (lsb first) after the start bit on the appropriate tv line, where den_ccf1 refers to field 1 and den_ccf2 to field 2. the tv line number where data is to be encoded is programmable using registers den_clf1 and den_clf2. lines that may be selected include those used by the starsight data broadcast system. closed-caption data has priority over any cgms signals programmed for the same line. the internal clock run-in generator is based on a direct digital frequency synthesizer. the nominal instantaneous data rate is 503,496 khz (i.e. 32 times the ntsc line rate). data low corresponds nominally to 0 ire, data high corresponds to 50 ire at the dac outputs. when closed-captioning is on (bits cc1 and cc2 in den_cfg1), the cpu should load the relevant registers (den_ccf1 or den_ccf2) once every frame at most (although there is in fact some margin due to the double- figure 144 rgb - chroma filtering 0 2 4 6 8 10 12 14 0 -5 -10 -15 -20 -25 -30 -35 -40 amplitude (db) frequency (mhz)
c o n f i d e n t i a l 20 digital encoder STI5518 208/294 7170179 d buffering). two bits are set in the den_sta register in case of attempts to load the closed-caption data registers too frequently; these can be used to regulate the loading rate. the closed-caption encoder considers that closed-caption data has been loaded and is valid on completion of the write operation into den_ccf1 for field1, or den_ccf2 for field 2. if closed-caption encoding has been enabled and no new data bytes have been written into the closed-caption data registers when the closed-caption window starts on the appropriate tv line, then the circuit outputs two us-ascii null characters with odd parity after the start bit. 20.15 cgms encoding cgms stands for copy generation management system , and is also known as vbid and described by standard cpx- 1204 of eiaj . cgms data can be encoded by the digital encoder. three bytes, containing 20 significant bits, are delivered to the chip via the register interface. two reference bits (1 then 0) are encoded first, followed by 20 bits of cgms data. this includes a cyclic redundancy check sequence, which is not computed by the device but is supplied to it as part of the 20 data bits. the reference bits are generated locally by the denc. figure 146 shows a typical cgms waveform. cgms encoding is enabled by setting bit encgms in register den_cfg3. when enabled, the cgms waveform is present once in each field, on lines 20 and 283 (smpte-525 line numbering). the cgms data register is double-buffered, which means that it can be loaded at any time (even during line 20/283) without any risk of corrupting cgms data that could be in the process of being encoded. the cgms encoder considers that new cgms data has been loaded and is valid on completion of the write operation into register den_cgms . figure 145 example of closed-caption waveform figure 146 example of cgms waveform 0 50 100 150 200 250 300 t lsb 61s 27.35s 13.9s 10s transition time : 220ns 7 cycles of 504khz 0 50 100 150 200 250 300 t lsb 11s 48.7s word 1 4 bits word 2 4 bits word 0 6 bits crcc 6 bits bit 1 bit 20
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 209/294 20.16 wss encoding the digital encoder allows wss (wide screen signalling) in 625-line format, complying with the ets 300 294 standard. two bytes are delivered to the circuit through the register interface into two dedicated registers (see register den_wss). wss encoding is enabled using bit enwss in register den_cfg3. when wss encoding is enabled, a waveform is present on the first half of line 23 of each frame. data is preceded by a run-in sequence and a start code generated locally by the denc. 20.17 vps encoding vps data encoding is defined by ets 300 231 communication, june 1993 . vps data can be encoded by the denc on line 16 (ccir) for 625-line pal and secam television systems. the vps data is delivered to the circuit using registers den_vps. the data transmission is preceded by a clock run-in and a start code generated by the denc. the clock frequency is 5 mhz. this feature is enabled by setting the envps bit of register den_cfg7. figure 147 shows an example of vps waveform. 20.18 teletext encoding the denc can encode teletext according to the ? ccir/itu-r broadcast teletext system b ? specification (also known as world system teletext), and nabts (north american basic teletext specification) eia-516. in dvb applications, teletext data is embedded within dvb streams as mpeg data packets. the transport layer processing ic (st20) sorts incoming data packets and stores teletext packets in a buffer. it then passes them to the denc on request. signal exchange the denc and the teletext buffer exchange 2 signals: ttxs (teletext synchronization) going from the denc to the teletext buffer and ttxd (teletext data) going from the teletext buffer to the denc. the ttxs signal is a request signal generated on selected lines. in response to this signal, the teletext buffer is expected to send teletext bits to the denc for insertion of a teletext line into the analog video signal. the number of teletext bits sent, depends on the teletext system being used (selected by register bit den_reg_64.ttxt_abcd) 360 bits are sent for teletext b - wst in pal and secam, or 288 for teletext c - nabts in ntsc. the duration of the ttxs window corresponds to the number of bits being sent (see transmission protocol below). figure 147 example of vps waveform lsbs run-in start data -code
c o n f i d e n t i a l 20 digital encoder STI5518 210/294 7170179 d for teletext b and 625 line systems, the ttxs window duration is 1402 reference clock periods (corresponding to 360 bits). for teletext c and 525 line systems (nabts), this duration is 1121 master clock periods. following the ttxs rising edge, the encoder expects data from the teletext buffer after a programmable number (2 to 9) of 27 mhz master clock periods. data is transmitted synchronously with the master clock at an average rate of 6.9375 mbit/s according to the protocol described below. in order of transmission, it consists of: 16 clock run-in bits, 8 framing code bits and one teletext packet of 336 or 228 bits (depending on the teletext system being used). if more than one packet of bits (336 or 228) are transmitted, they are ignored by the denc. by default, register bit den_reg_65. ttx_mask_off masks the two bits of teletext framing code, allowing the code to be set by the denc according to the selected teletext standard. transmission protocol in order to transmit the teletext data bits at an average rate of 6.9375 mbit/s, which is about 1 / 3.89 times the master clock frequency, the following scheme is adopted: the 360-bit packet is regarded as nine 37-bit sequences plus one 27-bit sequence. in every sequence, each teletext data bit is transmitted as a succession of four identical samples at 27 msample/s, except for the 10th , 19th , 28th and 37th bits of the sequence which are transmitted as a succession of three identical samples. programming ? ttxs rising ? to ? first valid sample ? the encoder expects the teletext buffer to clock-out the first teletext data sample on the (2+n) th rising edge of the master clock following the rising edge of ttxs. figure 148 depicts this graphically for n=0. n is programmable from 0 to 7 by register bits den_ttx1.ttxdel[2:0]. the value written in txdl[2:0] is 2 less than the overall delay in ckref cycles, so a value of 0 for txdl[2:0] corresponds to an overall delay of 2 cycles, and a value of 7 corresponds to a delay of 9 cycles. programming teletext line selection five dedicated registers, den_ttx1-5, program teletext encoding in various lines in the vertical blanking interval (vbi) of each field. in this way, each line in vbi can be selected independently. full-page teletext encoding is set by register bit den_ttx1.fp_ttxt. teletext is encoded on lines 24 to 311 and 336 to 623 (itu-r line numbering). this is in addition to the lines already programmed in the vbi. when full page teletext is performed, no video data is encoded (ycrcb, y4 and crcb input streams are ignored). figure 148 ttxt rising to first valid sample delay for txdl[2:0] = 0 not valid bit 1 bit 2 ckref ttxs ttxd (txdl[2:0]+2) t ckref
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 211/294 teletext pulse shape the shape and amplitude of a single teletext pulse is shown in figure 149 . its relative power spectral density is shown in figure 150 and figure 151 it is zero at frequencies above 5 mhz, as required by the world system teletext specification. figure 149 shape and amplitude of a single teletext symbol figure 150 linear psd scale figure 151 logarithmic psd scale 70 60 50 40 30 20 10 0 -100 -50 0 50 100 -144 ns +144 ns ire 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 1 0 2 3 4 5 6 7 8 frequency (mhz) psd (db) -10 0 -20 -30 -40 -50 -60 -70 -80 1 0 2345678 frequency (mhz) psd (db) normalized power spectral density (psd) of a single teletext pulse
c o n f i d e n t i a l 20 digital encoder STI5518 212/294 7170179 d 20.19 line skip and line insert capability this patented feature of the denc offers the possibility to cut the cost of the application by suppressing the need for a vcxo. ideally, the master clock used on the application board and fed to the mpeg decoding ic would have exactly same frequency as the clock that was used when the mpeg data was encoded. obviously this is not realistic; up to now a solution commonly used was to dynamically adjust the clock on the board as close to the ? ideal ? clock as possible with the help of time stamps embedded within the mpeg stream. such a kind of tracking often involves the use of a vcxo: when the mpeg data buffer fills up to more than some threshold the clock frequency is increased, when it empties down to some other threshold the clock frequency is lowered. the denc offers an alternative, cost-saving solution: by programming two bits in register den_cfg6, the denc is able to reduce or increase the length of some frames in a way that will not introduce visible artifacts (even if comb- filtering is used). these bits should be set according to the level of the mpeg data buffer. operation with the denc as sync master is as follows: if the mpeg data buffers fills up too much, set bit jump to 1 and bit dec_ninc to 1. the denc will reduce the length of the current frame. bit jump will then automatically reset to 0. if the mpeg data buffers empties too much, set bit jump to 1 and bit dec_ninc to 0. the denc will increase the length of the current frame. bit jump will then automatically reset to 0. these operations can be repeated until the mpeg data buffer is inside its fixed limits. line skip and line insert can be used in slave mode; the sync signals supplied to the denc must be in accordance with the programmed frame lengths. 20.20 cvbs, s-vhs, rgb and uv outputs six out of eight video signals can be directed to six analog output pins through a 10-bit d/a converters operating at the reference clock frequency. the available combinations are: s-vhs (y/c) + cvbs + rgb, or s-vhs (y/c) + cvbs + u + y2 + v, or y1 + c1 + cvbs1 + c2 + y2 + cvbs2. these combinations are controlled by bits conf_out1 and conf_out0 in register den_cfg8, as shown in the table below; the c to y peak to peak amplitude ratio can be modified in both cvbs and vhs (y/c) outputs (see mult_rgb_c). default peak to peak amplitude of uv and rgb outputs is set to 70% of y or cvbs peak to peak amplitude, for 100/0/ 100/0 color bar pattern, and can be modified using the multiplying factors in registers den_dac45 and den_dac6c. if den_cfg7[2] bit uv_lev is 0 (default value) u and v outputs have 0.7v peak to peak amplitude if 100/0/100/0 color bar pattern is inputted. if this bit is 1 u and v outputs are those defined by itu-r 624-4 for pal and ntsc standards (vpp/upp = 1.4). in that case u peak to peak amplitude is 0.61v (0.57v if den_cfg7 bit setupyuv is set) and v peak to peak amplitude is 0.86 v (0.80 v if register den_cfg7 bit setupyuv is set). in all these cases uv outputs can be multiplied by 0.75 to 1.22 factor according to register bits den_dac45.dac4_mult and den_dac6c.dac6_mult. a single external analog power supply pair is used for all dacs, but two independent pairs of current and voltage references are needed. a resistor must be connected between each i_ref and v_ref pins. conf_out1 conf_out0 dac1 dac2 dac3 dac4 dac5 dac6 notes 0 0 y c cvbs c y cvbs 01yccvbsvyu 1 x y c cvbs r g b default table 99 encoding of conf_out
c o n f i d e n t i a l STI5518 20 digital encoder 7170179 d 213/294 the internal current sources are independent from the positive supply, and the consumption of the dacs is constant whatever the codes converted. any unused dac may be independently disabled by software, in which case its output is at neutral level (blanking for luma and composite outputs, no color for chroma output, black for rgb and uv outputs). for applications where a single cvbs output is required, the rgb/cvbs+s-vhs/uv triple dac should be disabled, pin i_ref_dac_rgb should be tied to analog power supply and pin v_ref_dac_rgb should be left unconnected. due to the 2.5v power supply used, the output swing of the dacs is about 1vp-p. therefore some external gain may be required, which, combined with the recommended output filtering stage, means active filtering. for this active filtering stage to be very simple, it is possible to ? invert ? the dac outputs by programming a bit of den_cfg5. code n becomes code 1024-n, i.e. the resulting waveform undergoes a symmetry around the mid-swing code.
c o n f i d e n t i a l 21 teletext dma STI5518 214/294 7170179 d 21 teletext dma 21.1 introduction teletext data is retrieved from memory, serialized and transferred to the denc by a dedicated teletext dma. the denc encodes teletext data according to the ? ccir/itu-r broadcast teletext system b ? specification (also known as ? world system teletext ? ). 21.2 teletext packet format one teletext packet (otherwise called a teletext line) is a stream of 360 bits, transferred at an average frequency of 6.9375 mhz. the data format is the same as the contents of the pes data packet as defined in the etsi specification. the dma reads-in multiples of 46 bytes and transfers lines of 45 bytes to the denc. each teletext packet is composed of the clock run-in and the data-field, as illustrated in figure 152 . the clock run-in is composed of two bytes, each with the hexadecimal value #aa (binary value ? 10101010 ? ). the data-field consists of three fields: framing code, magazine and packet address, and data block fields. these three fields provide the block of teletext data. the framing code is a single byte of hexadecimal value #e4 1 . the data is transmitted in order, from the lsb to the msb of each byte in memory. 21.3 data transfer sequence the denc issues a teletext request signal to the teletext dma, this is shown by the rising edge of signal ttxtrequest in figure 153 . after a delay, programmable from 2 to 9 master-clock periods, the teletext dma transmits the first valid teletext data bit of the teletext packet. 1. specification for conveying itu-r systems b teletext in digital video broadcasting (dvb) bit-streams. figure 152 teletext packet format data field (43 bytes, 344 bits) 8 bits 16 bits 320 bits framing code magazine & packet address data block 10101010 10101010 clock run-in teletext line (45 bytes, 360 bits)
c o n f i d e n t i a l STI5518 21 teletext dma 7170179 d 215/294 the 360 bits of output data are defined as nine 37-bit sequences, ending with one 27-bit sequence. within each sequence, each bit is transmitted in four 27 mhz cycles, except bits 10, 19, 28 and 37, which are transmitted in three 27 mhz cycles. this is illustrated in the figure below for bits 0 to 10. the duration of the ttxs window is 1402 reference clock periods (51.926 s), which corresponds to the duration of 360 teletext bits (see transmission protocol below). the delay between signal ttxtrequest becoming high and the transfer of the first bit of the teletext packet is between 2 and 9, 27 mhz clock cycles. this delay is programmed by register bits den_ttx1.ttxdel[2:0]. the value written to this register is increased by two 27 mhz clock cycles, so the value 0 corresponds to an overall delay of 2x27 mhz clock cycles, and the value 7 corresponds to a delay of 9x27 mhz clock cycles. 21.4 interrupt control teletext interrupts can be programmed by the ttxt_intenable register to interrupt the cpu whenever one of the following occurs: a teletext data transfer is complete; the current video frame toggles odd-to-even or even-to-odd. the interrupt status is given by the ttxt_intstatus register and masked by the ttxt_intenable register. the interrupt bits are reset when the cpu writes to the acknowledge register, or when a dma operation is completed. 21.5 teletext registers five dedicated denc registers program the teletext encoding in various areas of the vertical blanking interval (vbi) of each field. four of these areas (i.e. blocks of contiguous teletext lines) can independently be defined within the two vbis of one frame (e.g. 2 blocks in each vbi, or 3 blocks in field1 vbi and one in field2 vbi, etc.). in certain circumstances it is possible to define up to 4 areas in each vbi. full-page teletext encoding is enabled by register bit den_ttx1.fp_ttxt. in this case, teletext is encoded on lines 7 to 311 and 320 to 623 (itu-r line numbering). if bit fp_ttxt_all is set, teletext encoding is also enabled on lines 6, 318 and 319. when full page teletext is performed, no video data is encoded (ycrcb, y4 and crcb input streams are ignored). figure 153 teletext data transfer sequence clock in, 27 mhz ttxtrequest teletext data invalid bit 1 bit 2 bit 10
c o n f i d e n t i a l 22 double triple video dac STI5518 216/294 7170179 d 22 double triple video dac 22.1 description there are two on-chip 3x10-bit digital-to-analog converters (triple dacs) used for video output. one provides output signals in cvbs, y, c, and the other in rgb. the figure below shows the dac schematic. an external reference resistor is associated with the bandgap voltage to generate a reference current. this resistor is connected between the v_ref pin of the bandgap and a dedicated i_ref pin to achieve a higher noise immunity. the global segmented architecture is presented in the figure below. current-sources provide an output range of 1.45v maximum with good linearity. sampled data are available on video outputs after 1 clock period (on the next rising clock edge). the triple video dac has its own 2.5v power and ground supplies for noise reduction. to guarantee good frequency response at high frequencies, these power and ground supplies are not connected to digital power supplies inside the chip. figure 154 double triple video dac schematic bandgap dac1 dac2 dac3 rref clock d1<9:0> d2<9:0> d3<9:0> from denc 1st triple dac y c cvbs bandgap dac4 dac5 dac6 rref 2nd triple dac red green blue d4<9:0> d5<9:0> d6<9:0>
c o n f i d e n t i a l STI5518 22 double triple video dac 7170179 d 217/294 22.2 input codes for video application the table below lists the reference input codes generated by the denc depending on the configuration for the dacs and the standard. note that cvbs = y+c, so chrominance component has no effect on cvbs signal (c is null) 22.3 video output voltage level the resistor rref connected to the bandgap has a direct effect on the output current which flows from the dac ? s outputs. for the maximum code (1023 in decimal): for example, with a typical value of rref = 20kohms, iout (max) = 4.04ma for each dac. the value of rref must be carefully chosen: iout should always be lower than 5ma, otherwise, dac linearity is not guaranteed. because of the sensitive relationship between the dac and rref, the tolerance on the rref value must be small. typically, the rref resistor must be a 1% resistor. the output voltage on the rgb output pins depends on the external load resistor rload (connected between the dac output and ground): for example, with a typical load value rload = 274ohms and iout(max) = 4.04ma, vout (max) = 1.11v. for any given digital input code, the output voltage of the dac will be given by the following formula: for example, with rload = 274ohms, rref = 20kohms and din = 526, vout = 0.57v y-pal/secam y-ntsc rgb white(235) 816.00 802.00 602.00 black(16) 256.00 240.00 41.00 sync tip 16.00 16.00 n.a. table 100 reference input codes iout (max) = 80.704 / rref vout (max) = rload * iout (max) vout = din / 1023 * vout (max) = ( din * rload * 80.704) / ( rref * 1023) vout = din * rload * 0.079 / rref
c o n f i d e n t i a l 22 double triple video dac STI5518 218/294 7170179 d 22.4 video specifications and dac setup in y-pal/secam, the output video range between code 16 (synchronization level) and code 816 (white level) should be: vout (816) - vout (16) = 1v. the output video range between code 256 ( black level) and code 816 ( white level) should be 700mv. this must be respected for all applications. the value of the rref resistor must be chosen according to the value of rload and the previous formula, to achieve the standard output video range. the minimum value for rref is 18kohms. according to video specifications itu-r bt 601, the nominal sampling frequency is 27 mhz. the clock for the dacs is the same as the one for the denc but buffered. this clock is usually generated externally by a vcxo. it must be as clean as possible to achieve a good signal-to-noise ratio. 22.5 output-stage adaptation and amplification a schematic of the output stage is shown below. the purpose of the output stage depends on the application and the required price-to-performance ratio. the output stage is connected directly to a scart connector or to other components (in which case the level and output impedance of the output signal may be different). the amplifier gain must be in accordance with the one of the tri-dacs (defined by rload and rref). if the amplifier gain cannot be set to the standard output video range by rref and rload, it can be tuned. in common applications (with rref=20kohms and rload=274ohms), a video amplifier should be adequate. the ideal input impedance of the output stage should be greater than rload. the tri-dacs have no cut-off frequency, therefore, a low-pass filter (around 10 mhz) must be applied to remove harmonics (of mainly 27 mhz). if additional attenuation is applied by the filter due to imperfection of the amplifier (generally degrading the c/l ratio), correction must be applied to preserve a good performance. also, to guarantee a good frequency behavior at high frequency, the analog power supply must be separate from the digital power supply. if this is not the case, an additional correction may be required. figure 155 output stage schematic tri-dac tri-dac r g b cvbs y c rref rref triple dacs rload output stage amplifier g=x low pass filter the output stage can be applied to any of the 6 tri-dac outputs scart STI5518
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 219/294 23 audio decoder 23.1 features input formats the audio decoder accepts: dolby digital, mpeg-1 layers i and ii, mpeg-2 layer ii 6-channel, pcm, cdda data formats; mpeg2 pes streams for mpeg-2, mpeg-1, dolby digital, mp3, and linear pcm (lpcm). spdif input data (iec-60958 or iec-61937 standards) is accepted if an external circuitry extracts the pcm clock from the stream. audio/video synchronization skip frame, repeat blocks and soft mute frame features can be used to synchronize audio and video data. pts audio extraction is also supported. output formats the device outputs up to 6 channels of pcm data and appropriate clocks for external digital-to-analog converters. 6 pcm data on three outputs: left/right, centre/subwoofer and left surround/right surround: dac_pcmout2-0; three clocks for the external dacs: dac_pcmclk, dac_sclk and dac_lrclk; programmable downmix enables 1, 2, 3 or 4 channel outputs. data can be output in either i 2 s format or sony format. the decoder can format output data according to iec-60958 standard (for non compressed data: l/r channels, 16, 18, 20 and 24-bits) or iec-61937 standard (for compressed data), for f s = 96 khz, 48 khz, 44.1 khz or 32 khz. sampling frequencies sampling frequencies (set by register aud_sfreq) of 96 khz, 48 khz, 44.1 khz, 32 khz and half sampling frequencies are supported. a down-sampling filter (96 khz/48 khz) is available. special modes the decoder supports dual mode for mpeg and dolby digital. it includes a dolby surround compatible downmix and a prologic decoder. a pink noise generator enables the accurate positioning of speakers for optimal surround sound setup. pcm beep tone is a special mode used for set-top box. it generates a triangular signal, of variable frequency and amplitude, on the left and right channels. in global mute mode, the decoder decodes the incoming bitstream normally but the pcm and spdif outputs are softmuted. this mode is used to prepare a period of decoding mode, to synchronize audio and video data without hearing the audio. virtual surround the 24-bit audio dsp cell supports trusurround, srs labs ? virtual technology for two-speaker playback of multi- channel audio. this reduces 6 channels of either dolby digital (ac-3) or mpeg multichannel audio to two channels only, providing to the user virtual multichannel sound effect. information on how to use this feature is sent to srs labs licensees only. trick modes slow-forward and fast-forward trick modes are available for compressed and non-compressed data.
c o n f i d e n t i a l 23 audio decoder STI5518 220/294 7170179 d control interface the control interface of the decoder is activated via memory mapped registers in the st20 address space. 23.2 architecture overview data flow the audio decoder has a programmable core, which is optimized for audio decoding algorithms. dedicated hardware performs bitstream depacking and iec data formatting. the figure below illustrates the audio decoder data flow. the compressed bitstream is transferred from the audio bit buffer (which is mapped into external (sdram) memory) to the audio decoder, via the mpeg dma, which filters a 64- byte fifo. when the fifo is filled, data are transmitted from the fifo to the audio decoder. the input processor (composed of a packet parser and an audio parser) unpacks the bitstream (packet parser) and verifies the syntax of the incoming stream (audio parser). the compressed audio frames with their associated information (pts) are stored into the circular frame buffer. while a second frame is stored in the circular frame buffer, the first frame is extracted by the audio core decoder and decoded into audio samples. the pcm-unit converts the samples to pcm format, and controls the channel delay buffer so that each channel can be delayed independently. simultaneously, the iec unit transmits non-compressed data or compressed data. in compressed mode, data is extracted directly from the circular buffer and formatted according to the iec- 61937 standard. in non-compressed mode, the left and right pcm channels formatted by the pcm unit are output by the iec unit, according to the iec-60958 standard. figure 156 architecture and data flow 1 data_in input data interface host interface control, status clocks 2 fifo 256 x 8 input processor circular frame buffer 3 4 core audio iec60958 formatter pcm unit channel delay buffer (35ms) decoder 6 7 8 iec-60958 (61937) out pcmout 5
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 221/294 figure 157 audio decoder block-diagram l r c lf e l s r s programmable switc h r c lf e l s r s l r c lf e l s r s l r l r switch packet formatter pt s iec958 formatte r mute pcm encode d pll and clock s pink noise generato r pc m dolby digital downmix l mpeg 1 mpeg 2 downmix bass redirection switch down- sampling 96/48kh z pes parse r parallel serial control microprocessor interfac e 1 2 3 4 fifo fifo 64bytes delay delay delay delay delay delay 52 54 53 dac_pcmout dac_pcmout1 dac_pcmout2 dac_sclk 51 56 55 dac_lrclk dac_pcmclk spdif_out 57 the switch has the following connections: 1-2: iec60958 not active 1-3: iec60958 (non-compressed data) 1-4: iec61937 (compressed data) data from sdram bit buffer prologic decoder l t r t 4 6 srs/trusurround volume pcm formatter mp3
c o n f i d e n t i a l 23 audio decoder STI5518 222/294 7170179 d 23.3 decoding process the decoding is performed in the following stages. each stage can be activated or bypassed by the configuration registers: 23.4 operation reset the audio decoder can be reset by software with the following two commands: softreset: to reset the audio decoder, ? 1 ? must be written in the register aud_softreset (0x10). the interrupt related registers (aud_inte, aud_int, aud_error) and command registers (aud_softreset, aud_run, aud_play, aud_mute, aud_skip_mute_cmd, aud_skip_mute_value) are reset to zero. the volume registers are reset to 0, no other decoding configurations are changed. the dsp returns to idle mode. reboot: a 1 must be written to bit reb of the aud_skip_mute_cmd register to reboot the audio decoder. registers aud_run, aud_play, aud_mute and aud_skip_mute_cmd are reset to 0. the dsp returns to idle mode. the decoding configurations are unchanged but 2 frames have to be sent to the decoder in order to perform the reboot. clocks the following clocks are used by the audio decoder: parsing bitstream parsing (performed by the input processor) discards all of the non audio information so that only the audio elementary stream (dolby digital, mpeg1/2, lpcm, pcm, dts, mp3) is transmitted to the next stage (the circular frame buffer).the parsing stage operates in two phases: the packet parser unpacks the stream, the audio parser checks the syntax of the bitstream. main decoding an elementary stream is input and decoded samples are output from this stage. the number of output channels is defined by the aud_downmix register (1 channel up to 6channels). dolby digital, mpeg1 layers i and ii, mpeg2 layer ii, lpcm, cdda, mp3 decoding formats are supported. the appropriate stream format must be set by registers aud_streamsel and aud_decodsel before running the decoder. post decoding post decoding includes specific pcm processing: dc filter, de-emphasis filter, downsampling filter. these filters can be independently enabled or disabled by the aud_dwsmode register. post decoding also provides a prologic decoder, described in prologic decoding modes on page 226 . the decoder output can also be processed according to srs labs trusurround algorithm. bass redirection this stage redirects low-frequency signals to the subwoofer. the subwoofer is extracted from the channels l, r, c, ls, rs, lfe. there are six configurations for subwoofer channel extraction, these are set by the aud_ocfg register. this is discussed in output configurations on page 229 . volume control the volume is controlled in steps of 1db, independently for each channel by the aud_chan_idx, aud_volume0 and aud_volume1 registers. table 101 audio decoding stages the pcm clock (dac_pcmclk signal) used by the external dacs to convert dac_pcmout0, 1, 2. it is usually generated by an embedded pll from the 27 mhz clock input. if necessary, it can be also be generated by an external pll. the internal frequency synthesizer can generate 256*fs or 384*fs where fs= 12, 16, 22.05, 24, 32, 44.1, 48, 96 or 192 khz. audio system pll the system pll creates the audio system clock from the 27 mhz input clock
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 223/294 23.5 decoding states there are two decoder states: idle state and decode state (see the figure below). the register aud_run changes the state. idle mode idle mode is entered after a hardware or software reset. in this mode, the embedded dsp does not decode, i.e. no data are processed, the chip is waiting for the run command. during this mode all configuration registers must be initialized. in idle mode, even if the chip is not processing data, the dacs clocks can be output, enabling the set-up of the external dacs. once the dac_pcmclk, dac_sclk and dac_lrclk clocks are configured, they can be output by setting the aud_mute register. note the play command has no effect in this state, as the decoder is not running. it can, however, be sent and it will be taken into account as soon as the decoder enters the decode state. bit clock dac_sclk the pcm serial clock is the bit clock. it provides clocks for each time slot (16 cycles for each channel in 16-bit mode, 32 cycles for each channel in 18-, 20-, 24-bit modes). the frequency of dac_sclk is, therefore, fixed to 2 x nb time slots x fs, where fs is the sample frequency. the clock is derived from dac_pcmclk. the register aud_pcmdivider must be configured according to the selected output precision and the frequency of dac_pcmclk, so that the device can construct dac_sclk:fsclk = fpcmclk / (2 x (aud_pcmdivider+1)) giving: aud_pcmdivider = (fpcmclk / (2xfsclk)) -1. word clock dac_lrclk the frequency of dac_lrclk is given by: flrclk = fsclk/32; for 16 bit pcm output, flrclk = fsclk/64; for 18, 20 or 24 bits pcm output. no special configuration is required. the polarity can be changed by the aud_pcmconf register bit inv (see pcm output on page 229 ). figure 158 decoding states play mute clock (dac_sclk, dac_ lrclk) state pcm output x 0 not running if play is set to 0 after reset. 0 x 1 running 0 table 102 idle mode, play and mute command effects idle mode init mode decode mode time run command decoder ready to play sample software reset, reboot or hardware reset
c o n f i d e n t i a l 23 audio decoder STI5518 224/294 7170179 d decode mode this state is entered after the run command has been sent (i.e. aud_run register = 1). in this mode, data is processed; the decoder can play sound, or mute the outputs by using the aud_play and aud_mute registers: to decode and output streams, the aud_play register must be set. if the aud_mute register is reset, the sound is sent to outputs; if the aud_mute register is set, the outputs are muted. note it is not possible to change configuration registers in this state, the chip must be soft reset beforehand. only the following registers can be changed ? on-the-fly ? : aud_chan_idx, aud_volume0, aud_volume1, aud_ ocfg, aud_ downmix registers. 23.6 stream parsers the synchronization status of both parsers is provided in the register aud_sync_status. each time the synchronization status of one of the two parsers changes, the interrupt syn is generated (if enabled) and the status can be read in aud_sync_status. packet parser the packet parser unpacks stream, sorts packets and transmits data to the audio parser. before unpacking packets and transmitting data, the packet parser must detect the packet-start by recognizing the packet synchronization word. the parser can be set to search for two packet synchronization words before starting to unpack and transmit, by setting the register aud_packet_lock to 1. otherwise, the packet parser will start handling the stream once it has detected information matching the packet synchronization word. the packet parser is also able to perform selective decoding, it can decode audio packets that match a specified id. this id is specified in aud_id and aud_id_ext registers, the function is enabled by setting the aud_id_en register. audio parser the audio parser verifies the stream syntax, extracts non audio data and sends audio data to the frame buffer. the audio parser must detect the audio synchronization word corresponding to the type of stream to be decoded. the audio parser can be set to detect more than one synchronization word before parsing, by setting the aud_sync_lock register to a value between 1 and 3. this number represents the number of supplementary sync words to detect before considering to be synchronized. 23.7 decoding modes dolby digital decoding modes the decoder must be programmed to specify the stream format as dolby digital encoded (in register aud_decodsel=0). reg. aud_play reg. aud_mute clock state pcm output decoding 0 0 not running 0 no 0 1 running 0 no 1 0 running decoded samples yes 1 1 running 0 yes table 103 decode mode. play and mute commands effects
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 225/294 the following modes refer to different implementations of the dialog normalization and dynamic range control features. the mode is selected by programming the register aud_ac3_comp_mod. mpeg decoding modes mpeg-1 layer1 and layer2 encoded data are decoded, as well as mpeg-2 layer2 data with or without extension (i.e. 6- channel streams). the mpeg input format must be specified in the aud_decodsel register: where aud_decodsel=1 for mpeg1 and aud_decodsel=2 for mpeg2. the dataflow is show in the figure below. dual-mode decoding modes in dual-mode, two completely independent mono program channels (e.g. bilingual) are encoded in the bitstream, referred to as channel 1 and channel 2. the left/right output is set to the following options by the aud_mp_dualmode register in mpeg format, and by the aud_ac3_dualmode register in dolby digital format: output channel 1 on both l/r outputs; line mode: in line mode (aud_ac3_comp_mod = 2), the dialog normalization is always enabled. it is done by the decoder itself and the dialog is reproduced at a constant level. the dynamic range control variable encoded in the bitstream is used and can be scaled by the two scaling registers aud_ac3_hdr (for high-level cut compression) and aud_ac3_ldr (for low-level boost compression). for 2/0 downmix, the high-level cut compression is not scalable. rf mode: in rf mode (aud_ac3_comp_mod=3), the dialog normalization is always performed by the decoder. the dialog is reproduced at a constant level. the dynamic range control and heavy compression variables encoded in the bitstream are used, but compression scaling is not allowed. this means that the aud_ac3_hdr and aud_ac3_ldr registers can not be used in this mode. an eleven db gain shift is applied on the output channels. custom 0 mode: in custom 0 mode (aud_ac3_comp_mod=0), the dialog normalization is not performed by the decoder and must be done by another circuit, externally. the dynamic range control variable encoded in the bitstream is used and can be scaled by the two scaling registers aud_ac3_hdr (for high-level cut compression) and aud_ac3_ldr (for low-level boost compression). custom 1 mode: in custom1 mode (aud_ac3_comp_mod=1), the dialog normalization is performed by the decoder. the dynamic range control variable encoded in the bitstream is used and can be scaled by the two scaling registers aud_ac3_hdr (for high-level cut compression) and aud_ac3_ldr (for low-level boost compression). figure 159 6-channel compressed data decoding flow data input interface fifo 256 bytes packet parser frame parser frame buffer dolby digital or mpeg decoder downmix bass redirection volume l r c lfe ls rs pcm_out0 pcm_out1 pcm_out2 6-channel compressed data l r c lfe ls rs l r c sub ls rs l r c sub ls rs delay delay delay delay delay delay
c o n f i d e n t i a l 23 audio decoder STI5518 226/294 7170179 d output channel 2 on both l/r outputs; mix channels 1 and 2 to monophonic and output on both l/r; output channel 1 on left output, and channel 2 on right output. pcm/lpcm decoding modes the decoder supports pcm and lpcm multi-channel streams, set by the register aud_decodsel=3. when decoding pcm/lpcm streams encoded at 96 khz, register aud_dwsmode configures the filter that downsamples the stream from 96 khz to 48 khz. note the device decodes the 6 channels of the dvd-lpcm stream, however, no downmix is possible. note for an 8-channel dvd-lpcm input file, only the 6 first channels are handled by the chip. the information contained in the 2 last channels is lost. prologic decoding modes prologic compatible downmix: a multichannel bitstream can be decoded and downmixed to provide a 2-channel prologic compatible output (lt, rt). this downmix is selected by the register aud_downmix. the 2 channels can be used as the input of a prologic decoder and player (e.g. home theatre). prologic decoding: a 2-channel prologic bitstream can be decoded. the 2 channels could come from a dolby digital 2-channel bitstream, a lpcm or an mpeg1 bitstream. the 2-channel bitstream can be converted into a 4-channel output (l, r, c, s). the surround (s) is simultaneously sent on ls and rs channels. a prologic downmix enables to configure which channels to output on pcm data. this is done through the register aud_pl_dwn. an auto-balance feature is available and activated through aud_pl_ab register. the delay on surround channel is configurable with the aud_lsdly register (while resetting the aud_rsdly register). the bass redirection is performed after the prologic decode. the same bass redirection configuration than those available in non-prologic modes can be used except that the surround channels will not be added to the bass figure 160 pcm/lpcm decoding flow data input interface fifo 256 bytes packet parser frame parser frame buffer 2-channel pcm/lpcm data downsampling filter 96 khz -> 48 khz l r volume, balance l r delay delay pcm_out0 pcm_out1 pcm_out2 zeros bass redirection l r sub sub delay zeros
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 227/294 redirection. in the case of dolby digital or mpeg, the dolby digital or mpeg stream can be decoded before the prologic decode. pink-noise decoding modes the pink noise generator is used to position the speakers in the listening room for optimum sound quality. figure 161 dolby digital & prologic decoding flow figure 162 mpeg & prologic decoding flow figure 163 pcm/lpcm & prologic decoding flow data input interface fifo 256 bytes packet parser frame parser frame buffer 2-ch dolby digital data, prologic encoded dolby digital decoder lt rt downmix bass redirection lt rt prologic decoder prologic downmix l r c s l r c s volume, balance pcm_out0 pcm_out1 pcm_out2 l r c sub s l r c sub s delay delay delay delay delay delay data input interface fifo 256 bytes packet parser frame parser frame buffer 2-ch mpeg1/2 data, prologic encoded mpeg1/2 decoder lt rt downmix lt rt prologic decoder prologic downmix l r c s l r c s bass redirection volume, balance pcm_out0 pcm_out1 pcm_out2 l r c sub s l r c sub s delay delay delay delay delay delay data input interface fifo 256 bytes packet parser frame parser frame buffer 2-ch pcm/lpcm data, prologic encoded downsampling filter lt rt prologic decoder prologic downmix l r c s l r c s 96 khz -> 48 khz bass redirection volume, balance pcm_out0 pcm_out1 pcm_out2 l r c sub s l r c sub s delay delay delay delay delay delay
c o n f i d e n t i a l 23 audio decoder STI5518 228/294 7170179 d the decoder is programmed to generate pink noise by writing the value 4 in the aud_decodsel register. the aud_downmix register selects the pink noise output channels. for pink noise generation, the register configuration should be: aud_ocfg=0 and aud_pcm_scale=0. note the appropriate pink noise level is obtained by attenuating all the outputs by 10db through volume registers. mp3 decoding mode mp3 supports the following frequencies in khz: 12,16, 22.05, 24, 32, 44.1 and 48. downmix, postprocessing, pcm delay and audio trick modes are not supported in mp3 mode. register aud_skip_mute_cmd cannot be used in mp3 mode. volume control is possible in this mode if register aud_ocfg is set to zero. figure 164 pink noise decoding flow figure 165 mp3 decoding flow pink pink noise generator noise downmix l r c lfe ls rs pcm_out0 pcm_out1 pcm_out2 no bass redirection: ocfg = 0 l r c lfe ls rs data input interface fifo 256 bytes packet parser frame parser frame buffer mp3 data mp3 decoder l r c s bass redirection volume, balance pcm_out0 pcm_out1 pcm_out2 l r c sub s l r c sub s pcm
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 229/294 23.8 pcm output output configurations figure 166 shows the different configurations supported by the pcm output stage. the configuration is set by the aud_ocfg register. in configuration 0, outputs are only scaled and rounded (see pcm scaling on page 230 ). in configuration 1, the main channels are attenuated by 15db, and the lfe by 5db before summing. after digital/analog conversion, the subwoofer pre-amplifier has to compensate for the different gains of the main channels and subwoofer. in configuration 2, the sub-woofer is optionally output. the signal for the sub-woofer is the processed sum of the centre and the surround channels (attenuated by 15db) and the lfe (attenuated by 5db). if it is not output, it is summed to the left and right channels. the left and right channels must be boosted by 12db either internally (register bit aud_ocfg.6) or externally (external amplifier). figure 166 pcm output configurations ls ls ll cc rr ls ls configuration 0 configuration 1 configuration 2 not used with prologic ll cc rr ls ls rs rs lfe sub -5db -15db rs rs lfe sub ll not used with prologic -12db cc rs rs lfe -5db -1.5db rr -12db l -8db/-4db c ls lfe r + l + -8db/-4db -4.5db c -8db/-4db r + -8db/-4db ls rs + -8db/-4db rs -8db/-4db sub off (normal) on (sub out) configuration 3 -15db on sub off
c o n f i d e n t i a l 23 audio decoder STI5518 230/294 7170179 d in configuration 3, the subwoofer is optionally output. if it is not output, all of the six input channels are attenuated by 8db. if the subwoofer is output, the attenuation is reduced to 4db. the outputs must then be boosted, by the amount of attenuation, either internally (register bit aud_ocfg.6) or externally (external amplifier). the same configurations are used for a decoded prologic program, with the exception that the surround channels are not added to the bass redirection (the surround channels of a prologic program are band limited and bass is considered as leakage). pcm scaling pcm scaling is required for every decoding mode. it is applied at the end of the filtering steps, before pcm output, allowing maximum effective word width for most of the signal processing before. independent volume for each channel is implemented for pcm scaling (registers aud_chan_idx, aud_volume0, aud_volume1). output quantization for 16/18/20-bit dacs, a quantization with rounding is applied together with the pcm scaling. the sample value is multiplied by a rounding factor and rounded to 24 bits. the result is then left-shifted (4/6/8) for pcm output. the output precision is selectable from the 16bits/word to 24 bits/word by configuring register aud_pcmconf[1:0]. interface and output formats the decoded audio data are output in serial pcm format. the interface consists of the following signals: output precision and format selection the pcm output is set in the aud_pcmconf register. output precision is set from 16 bits/word to 24 bits/word by register bit aud_pcmconf.prec. in 16-bit mode, data can be output either with the msb or lsb first, by setting register bit aud_pcmconf.ord. when aud_pcmconf.prec is set for more than 16 bits, 32 bits are output for each channel. in this configuration, register bit aud_pcmconf.for selects either sony or i 2 s compatible format, and register bit aud_pcmconf.dif positions the 18, 20 or 24 bits either at the beginning or at the end of each 32-bit frame. dac_pcmout0, 1, 2 pcm data - output dac_sclk bit clock (or serial clock) - output dac_lrclk word clock (or left/right channel select clock) - output dac_pcmclk pcm clock - input or output
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 231/294 the following figure and table describe the different output formats, and then 2 configuration examples are given: figure 167 output formats aud_pcmconf register settings data in sample memory data [23:0] 1 1. the internal 24-bit decoded, scaled and rounded audio samples are listed as they are stored in memory. these 24 bits are referred to as d23, d22,..., d0, where msb=d23, lsb=d0. data sent on the pcm serial output (left bit first) aud_pcmconf. prec aud_pcmconf. ord aud_pcmconf. for aud_pcmconf. dif 0:16-bit mode 1 na na {d23-d8}-{8*0} {d8-d23}: 16 bits 0:16-bit mode 0 na na {d23-d8}-{8*0} {d23-d8}: 16 bits 1:18-bit mode na 0 0 {d23-d6}-{6*0} {13*0}{0}{d23-d6}: 32 bits 1:18-bit mode na 0 1 {d23-d6}-{6*0} {0}{d23-d6}{13*0}: 32 bits 1:18-bit mode na 1 0 {d23-d6}-{6*0} {14*d23}{d26*d6}: 32 bits 1:18-bit mode na 1 1 {d23-d6}-{6*0} {d23-d6}{14*0}: 32 bits 2:20-bit mode na 0 0 {d23-d4}-{4*0} {11*0}{0}{d23-d4}: 32 bits 2:20-bit mode na 0 1 {d23-d4}-{4*0} {0}{d23-d4}{11*0}: 32 bits 2:20-bit mode na 1 0 {d23-d4}-{4*0} {12*d23}{d23-d4}: 32 bits 2:20-bit mode na 1 1 {d23-d4}-{4*0} {d23-d4}{12*0}: 32 bits 3:24-bit mode na 0 0 {d23-d0} {6*0}{0}{d23-d0}: 32 bits 3:24-bit mode na 0 1 {d23-d0} {0}{d23-d0}{7*0}: 32 bits 3:24-bit mode na 1 0 {d23-d0} {8*d23}{d23-d0}: 32 bits 3:24-bit mode na 1 1 {d23-d0} {d23-d0}{8*0}: 32 bits table 104 pcm output formats dac_lrclk dac_pcmout[2:0] dac_pcmout[2:0] dac_lrclk dac_pcmout[2:0] dac_pcmout[2:0] dac_pcmout[2:0] dac_pcmout[2:0] 16 dac_sclk cycles 16 dac_sclk cycles 32 dac_sclk cycles 32 dac_sclk cycles m s l s m s l s l s m s l s m s aud_pcmconf.ord = 0, pcmconf.prec is 16 bits mode aud_pcmconf.ord = 1, pcmconf.prec is 16 bits mode m s l s m s l s 00 m s l s m s l s 0 0 0 0 00 m s l s m s l s m s l s m s l s 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits msb msb aud_pcmconf.for = 1 aud_pcmconf.dif = 1 aud_pcmconf.for = 0 aud_pcmconf.dif = 0 aud_pcmconf.for = 0 aud_pcmconf.dif = 1 aud_pcmconf.for = 1 aud_pcmconf.dif = 0
c o n f i d e n t i a l 23 audio decoder STI5518 232/294 7170179 d configuration example 1: in 16-bit mode, with aud_pcmconf.ord=1: in memory, 24 bits are stored, where only the 16 msb bits (d23, d22,... to d8) are significant and the 8 remaining bits are 0. this is noted: {d23-d8} {8*0}. the data are sent lsb first, i.e. d8 is sent first and d23 is sent last. this is noted {d8-d23}. 16 bits only are transmitted per channel. configuration example 2: in 20-bit mode (aud_pcmconf.ord field is meaningless in this mode), with aud_pcmconf.for=1 and aud_pcmconf.dif=0: in memory, 24 bits are stored, where only the 20 msb (d23 to d4) are significant and the remaining 4 lsb are 0.this is noted: {d23-d4} {4*0}. 32 bits are transmitted per channel on the pcm outputs: the 12 first transmitted bits are d23, the last bits are d23 to d4, where d23 is transmitted first. this is noted: {12*d23} {d23-d4}. clock polarity the polarity of the pcm serial output clock (dac_sclk) and the pcm word clock (dac_lrclk) are selected by the fields scl and inv respectively, of the aud_pcmconf register. figure 168 shows the polarities of dac_sclk and dac_lrckl. the dac samples dac_lrclk and dac_pcmout on the rising edge of dac_sclk when aud_pcmconf.scl=0, and on the falling edge of dac_sclk when aud_pcmconf.scl=1. figure 168 dac_sclk and dac_lrclk polarity selection register configuration i 2 s format compatible outputs sony format compatible outputs aud_pcmconf.dif 1: not right padded aud_pcmconf.for 0: i 2 s format 1: sony format aud_pcmconf.inv 0: do not invert dac_lrclk 1: invert dac_lrclk aud_pcmconf.scl 0: do not invert dac_sclk 0: do not invert dac_sclk table 105 pcm configuration for i 2 s and sony compatible outputs dac_sclk dac_lrclk dac_pcmout0, 1, 2 scl = 0 dac_sclk dac_lrclk dac_pcmout0, 1, 2 scl = 1 dac_lrclk left right left right inv = 1 inv = 0
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 233/294 23.9 spdif output overview the spdif output pad is a ttl output pad with slew rate control. the output dc capability is 4 ma and the voltage drop is 3v. this output must be connected to a ttl driver before being connected to a transformer. the spdif output supports iec-60958 and iec-61937 standards. the following registers must be initialized to configure the spdif output: the category code must be entered in the aud_spdif_cat register. it is related to the type of application. the category code is specified in the digital output interface standard. the status bits that will be transmitted on the spdif output, must be programmed in the aud_spdif_status register. iec clock setting must be specified in the aud_spdif_conf register. the data type dependent information can be specified in the aud_spdif_dtdi register. the spdif type is selected through the aud_spdif_cmd register: the iec unit can output decoded data (pcm mode), encoded data, null data or pause bursts. when configured in iec-60958 mode, the spdif output is used to transmit the decoded left and right channels. the selection is done by choosing the pcm mode in the register aud_spdif_cmd and resetting the com status bit in aud_spdif_status register. if register bit aud_pcmconf[7] is set to ? 1 ? , 16 bits of data are sent, and if set to ? 0 ? , 24 bits are sent. when configured in iec-61937 mode, the spdif output is used to transmit encoded data taken directly from the frame buffer. the selection is done by choosing the encoded mode (enc mode) in the register aud_spdif_cmd and setting the bit com in aud_spdif_status register. the decompressed data are output simultaneously on the pcm_out outputs except in dts format for which only encoded data are transmitted. when choosing to output encoded spdif data, a latency is automatically inserted between spdif output and pcm outputs. the pcm outputs are delayed compared to the spdif output. the latency value is defined by standards and applied when the auto-latency mode is selected. when configured in muted mode (in the aud_spdif_cmd register), the outputs are pcm null data. this can be used to synchronize the external iec receiver. register aud_skip_mute_cmd bit mut is used to transmit bursts of pause frames in iec-61937 format. subcode into iec60958 user data user data bits are specified in the iec60958 specification. each iec60958 sub-frame contains 1 user-bit which can be used for subcode insertion in cd-da mode. a cd-da frame audio is 2352 bytes (pcm data) = 98 subframes of 24 pcm_data bytes associated with 98 subcode bytes. a subcode byte is defined by p,q,r,s,t,u,v,w bits with p bit always set to 1. alternatively p,q,r,s,t,u,v,w is included in iec60958 user data.
c o n f i d e n t i a l 23 audio decoder STI5518 234/294 7170179 d the input rate on iec60958 is one bit of user-data for 20 bits of pcm data, as illustrated in the figure below. the inclusion format of the subcodes into the user data is shown in the figure below. there are 8 bits of subcode for 12 bits of user data. that corresponds to 24 bytes of pcm-data if only 16 bits out of the 20 available bits are used. in vcd mode, subcodes are stored in the memory but not included on spdif output. data flow when the sector processor is used, it provides 96 subcodes bytes which are collected into a 128x16 bits word buffer. 16 bits of subcodes can be read through the fei_sub register. at the end one sector transfer (signalled with it eos), 96 bytes of subcodes can be accessed by reading the subcodes register address 48 times. these 48 values of 16-bits can be stored in the memory-subcode-buffer. the register fei_sff detects the filling level of the fifo (in the number of 16 bits word). note to prevent st20 hang-up, verify that the subcode buffer is not empty by using fei_sff before reading the subcodes with register fei_sub. after processing one sector, the track buffer contains linear pcm samples (dma transferred) and the memory subcode buffer contains related subcodes (micro transferred). to synchronize the pcm and subcode, the st20 reads pcm data from track buffer, and subcode from the memory subcode buffer. it then interleaves 98 bytes of subcode and 2352 pcm bytes into the audio bit buffer. figure 169 iec60958 sub-frame format figure 170 subcode insertion in iec6958 figure 171 audio bit buffer content sync_preamble l s b aux. l s b audio sample word m s b vucp 03478 272831 validity flag user data channel states parity bit 001qrstuvw0 0 123456789101112 subcode inclusion format from the specific stream 4 zeros automatically inserted by the audio cell. 32 bits word dsc 24 words of subcodes 588 words of pcm data dsc ... sc(i) is a subcode byte 96 bytes of subcodes 2352 bytes of pcm_data key
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 235/294 a dummy start code (dsc) of 24 + 8 bits is inserted (by the st20) into the audio bit buffer to secure the input in audio macrocell. in this case the first word which follows this dsc is guaranteed to be a subcode word. assumption1: the first pcm sample is supposed to be always a left sample. assumption2: a cd-da pcm sample is 16 bit. pcm_data in dvd: a normal mode without subcodes insertion is available to input pcm_data into the macrocell (for pcm_data in dvd mode). this is the global mechanism to input subcodes into the macro-cell (see figure below) 23.10 interrupts interrupt register the audio decoder contains a 16 bit interrupt register aud_int associated with a 16 bit ? enable ? register aud_inte. a bit set in register aud_inte enables the corresponding interrupt. the interrupt associated with each bit is given in the register aud_int description. according to the type of interrupt, other information such as stream header, type of error detected, pts value, can be obtained by reading associated registers error concealment errors are signaled as interrupts by the audio core. most of the errors are automatically handled by the core, but some require that software change. error categories are defined in the aud_error register description in the device register manual. figure 172 specific audio input stream figure 173 cd_da and subcode data flow without subcode 0xcc 0xcd 0xda 2352 bytes 0x00 1 byte 3 bytes key dummy start code (dsc) pcm data with subcode 0xcc 0xcd 0xda 2352 bytes 0xff 1 byte 96 bytes 3 bytes key dummy start code (dsc) subcodes pcm data external sdram sin audio macrocell track buffer memory subcode buffer audio bit buffer st20 16 bits register dma pcm data 32 bits 2x128 fifo subcode sector processor
c o n f i d e n t i a l 23 audio decoder STI5518 236/294 7170179 d dolby digital decoding errors are signaled in the aud_error register but handled directly by the core. these errors cannot be changed by software. dolby digital decoding errors signal that something went wrong during decoding. the core soft-mutes the frame and continues to decode. mpeg decoding errors are signaled in the error register but are handled directly by the core. nothing can be done by the software. they signal that something wrong happened during the decoding. the core soft-mutes the frame and continues to decode. only one error in this category indicates a programing error: if triggering the mpeg_ext_crc_error, the bit mc_off must be set. this indicates that the decoder tries to decode more than 2 channels whereas the incoming stream contains only 2 channels. packet and audio synchronization errors are handled internally and usually indicate that the incoming bitstream is incorrect or that it has been incorrectly input to the chip. in these cases, the decoder resets the corresponding parsing stage (packet or audio parser) then searches for the next correct frame. miscellaneous errors such as the latency_too_big error indicate a problem of latency programming which is superior to the maximum authorized value. the latency value should be changed or a switch made to auto-latency mode. other miscellaneous errors are handled internally. 23.11 audio/video synchronization presentation time stamp detection when enabled through the inte register, the interrupt pts is generated when a pts is present in the frame that is being output on dac_pcmout (the interrupt is fired when the first decoded samples of the first block of the frame is output). pause frames capability the number of audio blocks for the audio decoder to pause must be programmed in register aud_skip_mute_value. then bit blk of the aud_skip_mute_cmd register must be set. the audio decoder will finish decoding the current frame, softmute the next frame, and pause for the number of blocks specified in aud_skip_mute_value. when the pause is finished, decoding continues. skip frames capability the number of frames to skip must be programmed in register aud_skip_mute_value. then bit skp of the aud_skip_mute_cmd register must be set. the audio decoder will finish decoding the current frame, softmute the next frame, and skip the number of frames specified in aud_skip_mute_value. after skipping, it resumes decoding from the next incoming frame.
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 237/294 pause burst capability to synchronize video and audio outputs, the audio cell must be able to insert a pause on the output when required. this means that the audio decoder has to stop before decoding a new frame and the output of the audio has to be muted for a period of time as illustrated below. a pause is initiated by register aud_skip_mute_cmd: if bit skip_mute_cmd.pau is set, a pause is inserted until bit pau is reset. if register bit aud_skip_mute_cmd.blk is set, a pause burst is inserted for a duration set by the value in register aud_skp_mute_value. the granularity of the gap defined by this mechanism is: 256 sampling periods for ac-3 (5.3ms at 48 khz - 5.8ms at 44.1 khz) 96 sampling periods for mpeg (2ms at 48 khz) 23.12 pcm beep tone description pcm beep tone is a special mode used for set top box. it generates a triangular signal of variable frequency and amplitude on the left and right channels. activating pcm beep tone mode to active this mode: reset the dsp set-up the registers aud_decodesel (0x4d) = 7 and aud_streamsel (0x4c) = 3 restart the dsp by asserting register aud_run and aud_play figure 174 pause burst capability illustration video angle 1 video frame v11 v12 v13 v14 v15 audio frame a1 a2 a3 a4 a5 a6 a7 video angle 2 video frame v22 v22 v23 v24 v25 video input with change of angle video frame v11 v12 v13 v24 v25 audio frame a1 a5 a6 a7 gap of n ms a2 a3 a4 change of angle for instance
c o n f i d e n t i a l 23 audio decoder STI5518 238/294 7170179 d changing the frequency set register aud_pcm_btone (0x68) according to the equation below: changing the amplitude the amplitude of the pcm beep-tone is 0db by default, to change the amplitude set the registers below: aud_ocfg (0x66) = 0 aud_chan_idx (0x67) = 0 (to select the channel pair (left and right) aud_volume0 (0x4e) = attenuation value (step of -1db) on left channel aud_volume1 (0x63) = attenuation value (step of -1db) on right channel the pcm beep-tone can be sent to the spdif output when the spdif output is configured in pcm mode. 23.13 audio trick modes 23.13.1 description audio trick modes accelerate or slow-down the audio in analogue audio systems. slow and fast forward are described in this section. 23.13.2 slow forward audio play-back is slowed-down by copying the same sample two or three times into the ram of the pcm output block. this method is managed by the embedded software and is independent of the dsp speed. however, it is dependent on ram size and, as shown in figure 175 , only the left and right channels can be processed for slow forward. to obtain all of the audio information on the left and right channels, a dolby surround compatible downmix must be done before the trick mode is carried out (configuration 2/0 dolby surround of the downmix). beep_tone frequency = (fs/2) / (register_value + 1) figure 175 expanding audio samples for the trick-mode ? slow forward ? ram 256 samples 256 samples 256 samples 256 samples 256 samples rightsurr leftsurr lfe center right left 256 samples before expand audio samples ram 512 samples left 512 samples after expand x2 audio samples right pcm block hardware pcm_out0 only
c o n f i d e n t i a l STI5518 23 audio decoder 7170179 d 239/294 due to the change of pcm block size, prologic decoding and srs process must be disabled in slow-forward mode. volume control and bass redirection are allowed. the aud_tm_speed register can be configured in the following ways: aud_tm_speed = 0: normal speed, aud_tm_speed = 1: slow forward (twice slower), aud_tm_speed = 2: very slow forward (three times slower). 23.13.3 fast forward this mode is implemented differently for compressed and non-compressed data. the fast-forward register configuration is identical for non-compressed and compressed algorithms. fast forward on compressed algorithms (ac3, mpeg1&2 and dts) for compressed algorithms, the audio cell receives data in units of frames which correspond to a duration of approximately 30ms on the pcm output after decoding. the data flow is illustrated below: in normal mode (non fast-forward mode), the audio parser sends all of the complete frames to the frame buffer. in fast-forward mode, the audio parser can be configured to send alternate frames (1 in 2) or every third frame (1 in 3) to the frame buffer to be decoded. fast-forward mode creates discontinuity between each pcm block of samples because the decoder looses the dependency of the missing frames. post-processing is used to harmonize consecutive frames. fast forward on non-compressed algorithms (lpcm, pcm & cdda) for these formats, whole frames are handled but samples are skipped at the output. to play 2x faster, 1 sample out to 2 is played; to play 3x faster, 1 sample out of 3 is played. register configurations the speed is set by the aud_tm_speed register configurations below: aud_tm_speed = 0: normal speed, aud_tm_speed = 0x80: fast forward (two times faster), aud_tm_speed = 0x40: very fast forward (three times faster). to update this mode in the dsp, write the value 2 in the aud_update register. figure 176 data flow fast-forward mode on compressed audio algorithms packet-parser audio-parser frame buffer dsp core ram pcm_output data_in
c o n f i d e n t i a l 23 audio decoder STI5518 240/294 7170179 d 23.13.4 spdif output for audio trick modes the table below summarizes the spdif output for audio trick modes: spdif output mode non-compressed data compressed data ac3, mpeg1&2, dts in slow mode ok does not work ac3, mpeg1&2, dts in fast mode ok ok lpcm, pcm, cdda in slow mode ok na lpcm, pcm, cdda in fast mode ok na table 106 spdif output for audio trick modes
c o n f i d e n t i a l STI5518 24 external audio decoder interface 7170179 d 241/294 24 external audio decoder interface the STI5518 can be connected to an external audio decoder development platform via the external audio decoder interface. the interface to an external audio decoder is composed of two buses: a synchronous serial interface for compressed data transfer; a control interface through the i 2 c and programmable cpu interface. this chapter describes the synchronous serial interface. its four signals are described in the table below, and a schematic of the external audio decoder interface is shown in the figure below.. ext_aud_req is active when the external audio decoder is capable of accepting data and ext_aud_clk is used to strobe the data into the audio decoder on the rising edge. the signal ext_aud_wclk is the ext_aud_clk signal divided by 32. it is phased so that the transition coincides with a byte boundary. this signal can be used as a framing signal for certain external audio decoders. when the external audio decoder interface is crossed, there is no internal limitation on the format of the data that is transferred from the audio bit-buffer to the external decoder. the ext_aud_clk frequency can be either internal clock clock2 or internal clock clock3 (equal to clock2/2). this is set by register vid_cfg_gcf bit sck. external audio decoder interface signal name signal name pin no type description ext_aud_data dac_pcmout0 52 out packet data ext_aud_clk dac_sclk 51 out packet strobe ext_aud_req dac_pcmout1 53 in data request ext_aud_wclk dac_lrclk 56 out word clock table 107 external audio decoder interface signals figure 177 external audio decoder interface schematic audio read fifo data 64 aud_req dac_pcmout0 dac_sclk dac_lrclk /32 signal mux signal mux aud_wclk aud_data aud_clk dac_pcmout0 / STI5518 audio decoder ext_aud_data dac_sclk / ext_aud_ckl dac_lrclk / ext_aud_wclk dac_pcmout1 / ext_aud_req audio bit buffer shared memory sdram dac_pcmout1 internal to the device external to the device
c o n f i d e n t i a l 25 clock generator STI5518 242/294 7170179 d 25 clock generator 25.1 introduction all of the clocks are generated in this clock generator block, and can be defined in the following groups: system clocks based on a single pll. the system pll multiplies the 27 mhz input clock to generate a common multiple frequency for the st20 processor, dvd i/f block (link and fei), mmdsp audio block and the video block (including the sdram clock). pcm clock, generated by a digital frequency synthesizer. this is part of the clock generator block, although situated in the audio block for optimum performance. smartcard clock, based on a digital frequency synthesizer included in the clock generator. auxiliary clock, provided by a digital frequency synthesizer included in the clock generator. low-power, watchdog and power-down. the system clock frequencies given in this chapter are the default frequencies. for selecting other operating frequencies see the applications note "STI5518 clock management and over-clocking".
c o n f i d e n t i a l STI5518 25 clock generator 7170179 d 243/294 the figure below illustrates pll and frequencies synthesizer configurations and the device clock distribution. 25.2 system clocks all of the system clocks are generated from the system pll and integer dividers, with no need for external dividers and pll circuitry. the reference input frequency is the 27 mhz clock. this reference is multiplied by an integrated pll, and the pll output is steered to a bank of 5 dividers. the table below summarizes the system clocks. figure 178 STI5518 pll and frequency synthesizer configuration clock default value (mhz) common value (mhz) comment input clock 27 27 x 9 by internal pll = 243 mhz video 27 60.75 generate internal clk2 and clk3 sdram 27 121.5 programmable between 100 and 125 mhz to improved band width tpmac 60.75 60.75 programmable between 60 and 81 mhz. table 108 system clocks summary st20 cpu dvd interface 2 4 60.75 mhz 60.75 mhz 27 mhz dacs dacs smc clock aux clock clock generator video decoder audio decoder pal/ntsc/secam encoder pll pcm clock 121.5 mhz pix_clk (pin 120) b_bclk (pin 17) smi_clkin (pin82) smi_clkout (pin95) dac_pcmclk (pin 55) 2 121.5 mhz 60.75 mhz
c o n f i d e n t i a l 25 clock generator STI5518 244/294 7170179 d each system clock can be bypassed (output clock = bypass clock), enabled (the output clock is turned off), and divided by 2, separately. this is determined by the value programmed in the respective control registers; the table below gives the recommended divider values. the pll lock state is readable, and the pll reset is programmable. the system pll multiplies the 27 mhz input clock, the output frequency is calculated as below, where n=162, m=18, p=1 for fpll = 243 mhz: where the values of m, n and p must satisfy the following constraints: 25.3 pcm clock the pcm clock frequency synthesizer generates the dac clocks for the audio decoder. after hard reset, the pcm clock pins are inputs to the device. when the aud_pllpcm register is set, the pcmclk clock becomes an output. the table below shows the values which must be written by the st20 to obtain the pcmclk. fei 60.75 60.75 same reference as tpmac clock link core 60.75 60.75 same reference as tpmac clock denc 27 27 from input clock uart 27 60.75 normally derived from cpu clock (st20 internal divider). audio (mmdsp) 27 60.75 low power clock 212 khz 212 khz 27 mhz divided clock (pll frequency, f (clockout) = 243 mhz) reset value frequency divider register value sdram clock (ckg_div_mck) 27 121.5 0x01 st20(ckg_cnt_st20, ckg_div_st20), fei & link 60.75 60.75 0x02 mmdsp (ckg_div_aud) 27 121.5 0x01 table 109 recommended divider values clock default value (mhz) common value (mhz) comment table 108 system clocks summary f clockout () 2 n m 2 p ---------------- - f clockin () = 1 m 255 1 n 255 0 p 5 ? , ? , ? 1 mhz f clockin () m --------------------- - 2 mhz ? 200 mhz 2 n m ------------ - ?? ?? f clockin () 622 mhz ? f clockin () 200 mhz
c o n f i d e n t i a l STI5518 25 clock generator 7170179 d 245/294 the audio clock frequency synthesizer uses the registers ckg_sfreqaud_sdiv, ckg_sfreqaud_pe and ckg_sfreqaud_md and aud_pllmask to program the frequency. table 110 lists the register settings versus audio frequency values. register ckg_sfreqaud_cnt selects which controller is used. 25.4 smartcard clocks the directv smartcard frequency is 18.436 mhz, the register values given in the table below must be used to achieve this frequency. 25.5 auxiliary clock the auxiliary clock operates over the frequency range 1-216 khz, in 1 khz steps. the table below gives example values for programing the auxiliary clock. frequency register values in hex aud_pllmask bit half_fs ckg_sfreqaud_sdi v (0x1e4) ckg_sfreqaud_md (0x1e7) ckg_sfreqaud_pe (0x1e5, 0x1e6) 384 x 32 khz 80 88 3600 0 384 x 44.1 khz 60 c8 3eb2 0 384 x 48 khz 60 b8 4800 0 256 x 32 khz 80 d0 5100 0 256 x 44.1 khz 80 98 6f05 0 256 x 48 khz 80 88 3600 0 256 x 96 khz 60 88 3600 0 384 x 96 khz 40 b8 4800 0 256 x 12 khz c0 88 3600 0 384 x 12 khz a0 b8 4800 0 384 x 16 khz 80 88 3600 1 384 x 22.05 khz 60 c8 3eb2 1 384 x 24 khz 60 b8 4800 1 256 x 16 khz 80 d0 5100 1 256 x 22.05 khz 80 98 6f05 1 256 x 24 khz 80 88 3600 1 table 110 pcm frequency values and register settings frequency (mhz) ckg_sfreqsmc_sdiv (hex) ckg_sfreqsmc_md (hex) ckg_sfreqsmc_pe (hex) 18.436 31748a7 frequency (mhz) ckg_sfreqaux_sdiv (hex) ckg_sfreqaux_md (hex) ckg_sfreqaux_pe (hex) 17 1a 0 26 1a 0 3 6 12 8000 45 1a 0 table 111 auxiliary clock programming values
c o n f i d e n t i a l 25 clock generator STI5518 246/294 7170179 d 25.6 low-power, watchdog and power-down low-power the low-power timer is a 64bit counter which is always clocked, even when the other internal clocks are stopped. the low-power clock is generated from the 27 mhz input and is divided by the value (2 multiplied by the value programmed into register ckg_div_lpc). the lpm_timerstart register, starts the low-power timer controller. watchdog counter the low-power alarm counter can be used as a watchdog timer if register lpm_wdenable bit 0 is set. this makes it impossible to enter low-power mode when starting the low-power alarm counter. to trigger the watchdog, the low-power alarm is programmed and started as normal. when the low-power alarm counts down to the value #1, the circuit resets.the lpm_wdflag register is set when a watchdog reset occurs. power-down in power-down mode the internal clocks are turned off, the processor and ll of the peripherals, including the external memory controller and optionally the pll, are stopped. effectively, the internal clock is stopped and functional operation is stalled. on restart, the clock is restarted and the chip resumes normal operation. the pll is turned on and off using the lpm_syspll register provided that there are no active external interrupts, power-down is entered when low-power alarm counter lpm_alarmstart is programmed and started. power-down is exited when an enabled external interrupt becomes active, or when the low-power alarm counter reaches zero. the low-power alarm counter is a 40-bit counter which triggers power-down mode. a write to the lpm_alarmstart register starts the low-power alarm counter and the device enters low-power mode. when the counter has counted down to zero, and assuming no other valid wake-up sources occur first, the device exits low-power mode and the global clocks are turned back on. in power-down mode the st20 pll can be left running, it can be partially turned off (power and reference still on) or it can be completely turned off. this is determined by the value in the lpm_syspll register. the mpeg pll can be turned off if required during power-down mode. 5 5 15 3333 10 4 15 3333 15 3 1c 199a 20 3 15 3333 25 3 11 5c29 30 2 1c 199a 35 2 18 283b 40 2 15 3333 45 2 13 6666 50 2 11 5c29 55 1 1f 4a79 60 1 1c 199a frequency (mhz) ckg_sfreqaux_sdiv (hex) ckg_sfreqaux_md (hex) ckg_sfreqaux_pe (hex) table 111 auxiliary clock programming values
c o n f i d e n t i a l STI5518 26 mpegdma controller 7170179 d 247/294 26 mpegdma controller the mpegdma copies blocks of data from one memory address to an internal or external mpeg device. the source address, destination address and the number of bytes must be specified in the mpegdma registers. there are two groups of mpegdma registers used for video, audio and subpicture data transfers, mpegdma0 and mpegdma1. an mpegdma data transfer is initiated by placing source address and destination device values into the mpegdman_srcadd, mpegdman_burstsize and mpegdman_whichdec registers respectively, and then writing a byte count value into mpegdman_blsize register to start the data transfer process. when the data transfer is complete an interrupt is generated, its value can be observed in the mpeg_status register. this interrupt can be enabled onto the external per_interrupt bristle for transmission to an interrupt controller, etc. by setting bit 0 in mpegdman_cntrl register. no further data transfers can be started until the interrupt has been cleared by writing to the mpegdman_intack register. while a data transfer is in progress, the mpegdman_cntrl and mpegdman_status registers can be accessed, and no further operations can be started by writing to mpegdman_blsize. at any time during a data transfer operation the process can be stopped by writing to the mpegdman_abort register. this stops the data transfer and resets the dma engine. the busy flag in the mpegdman_status register can be polled to determine whether the dma engine is ready for further instructions. the mpegdma registers are accessed by bits 2 to 5 of the dmacnt_and_peraddr (peripheral address) inclusively. the table below summarizes the mpegdma registers, these are described in detail in the STI5518 register manual. register address width access notes mpegdman_burstsize base + 0x00 5 w the number of bytes to be transferred in one burst mpegdman_holdoff base + 0x04 5 w holdoff for mpeg decoder: range 0 to 31, where 0=0 delay cycles mpegdman_abort base + 0x08 1 w abort all operation mpegdman_whichdec base+ 0x0c 2 w dma destination pointer mpegdman_status base + 0x10 2 r interrupt status register mpegdman_intack base + 0x14 1 w interrupt acknowledge register mpegdman_srcadd base + 0x18 32 w dma source pointer mpegdman_cntrl base + 0x1c 2 r/w interrupt control register mpegdman_blsize base + 0x20 16 w data block dimension to be transferred table 112 mpegdma registers
c o n f i d e n t i a l 27 block move dma STI5518 248/294 7170179 d 27 block move dma this module copies blocks of data from one byte address in memory to another. the module can only access memory. a source address, a destination address and a count of the number of bytes to be transferred must be specified. the interface between the cpu and the block move module is provided using a set of registers and an interrupt. the interrupt signals when a dma transfer has completed. to perform a dma block move from one memory buffer to another, the block move module must first be initialized with the source and destination addresses and then a byte count written to the bmdma_count register, to specify the amount of data to transfer and start the dma operation. the source and destination addresses are the bases of the source and destination areas and can be any byte addresses. the transfer size can be any value in the range of 1 to 65535 bytes. if the source area overlaps with the destination area, then the result is undefined. at the end of the block move operation the bmdma_status register will signal that an interrupt is pending. if the interrupt enable bit of the bmdma_inten register is set to 1, this will cause an interrupt. the interrupt pending bit must be reset by software which writes to the bmdma_intack register, before any further block move operations can be performed. a dma block move can be aborted by writing to the bmdma_abort register.
c o n f i d e n t i a l STI5518 28 pwm and counter module 7170179 d 249/294 28 pwm and counter module this module provides three pwm encoder outputs, three pwm decoder (capture) inputs and four programmable timers. each capture input can be programmed to detect rising edge, falling edge, both edges or niether edge (disabled). these facilities are clocked by two independent clocks, one for pwm outputs and one for capture inputs/ timers. the module generates a single interrupt signal. the exact event which caused an interrupt can be determined by reading status bits in a register, which can then be cleared. for pwm0 and pwm2 to act as outputs the denc must operate in master mode. to set the denc to master mode, set register den_cfg0=xx11 0xxx. 28.1 external interface 28.2 pwm outputs there are four pwm outputs which share a common counter. the relative width (in counts) of the output pulse on pin pwm n is set between 1 and 256 by loading a value from 0 to 255 into the register pwm_nval . the width cannot be less than 1, and if it is 256 the pin is continuously high. pulses occur every 256 counts. the counter is clocked by the 27 mhz clock clockin divided by a prescaler. the prescaling factor, and therefore the period represented by one count, is determined by the value of register pwm_controlfield.pwmclkvalue. the factor can be from 1 to 16. the counter (in register pwm_count) is enabled by setting the register pwm_controlfield.pwmenable to 1. when it is disabled (pwmenable is 0), the pwm output is forced low. register pwm_count can be written to at any time, but can have a synchronization latency. when the pwm counter overflows, an interrupt is generated if register bit pwm_intenable.inten is set to 1. register bit pwm_intstatus.int becomes 1, and can be reset by writing 1 to register bit pwmintack.intack. 28.3 capture inputs there are four capture inputs which share a common counter with four compare facilities. what constitutes an event on input capturein n is defined by the code in register pwm_ncaptureedge. possible events are rising edge, falling edge, both or neither (in other words, disabled). when an input event occurs on input pwm_ncaptureedge, the value of the counter (in register pwm_ncapturecount) is captured in register pwm_ncaptureval. the value can be 0x00000000 to 0xffffffff. when an input event occurs, an interrupt is generated, provided that the register bit pwm_intenable.inten is set to 1. register bit pwm_intstatus.intn becomes 1, and can be reset by writing 1 to register bit pwm_intack.ack n . the counter is not stopped nor reset by any of these events. see capture/compare counter, prescaling and clocking on page 250 for details. name in/out function pwm0, pwm1, pwm2 out pwm outputs capture_in0,capture_in1, capture_in2 in capture trigger inputs comp_out0, comp_out1 out compare output table 113 pwm and counter pins
c o n f i d e n t i a l 28 pwm and counter module STI5518 250/294 7170179 d 28.4 compare (programmable timer) facilities there are four programmable timer facilities which share a common counter with four capture inputs.each of four compare registers pwm_ncompareval in the module can be set to a value 0x00000000 to 0xffffffff. when the counter in register pwm_capturecount reaches the value of register pwm_ncompareval, two things happen: an interrupt is generated if register bit pwm_intenable.inten is set to 1. register bit pwm_intstatus.int n becomes 1, and can be reset by writing 1 to register bit pwm_intack.ack n . pin pwm_ncompareout takes on the value set in register pwm_ncompareoutval . the counter is niether stopped nor reset by any of these events. see capture/compare counter, prescaling and clocking on page 250 below for details of the counter. 28.5 capture/compare counter, prescaling and clocking the capture/compare counter is clocked by the prescaled system clock, and is common to all capture and compare functions. the prescaling factor, and therefore the period represented by one count, is determined by the value of register bit pwm_control.captureclkvalue. the factor can be from 1 to 32. the counter (in register pwm_capturecount) is enabled by setting register bit pwm_control.captureenable to 1. when it is disabled (pwm_control.captureenable=0), none of the capture or compare functions work. pwm_capturecount, like pwm_count, can be read or written to at any time. when the capture/compare counter reaches its maximum count of 0xffffffff, it wraps round to count up from zero again.
c o n f i d e n t i a l STI5518 29 smartcard interface 7170179 d 251/294 29 smartcard interface the smartcard interface supports asynchronous protocol smartcards as defined in the iso7816-3 standard. limited support for synchronous smartcards can be provided in software by using the pio bits to provide the clock, reset, and i/o functions on the interface to the card. two smartcard interfaces are supported on the STI5518. the uart function of the smartcard interface is provided by a uart (asc). uart asc0 can be used by smartcard0 and asc2 can be used by smartcard1. each asc used by a smartcard interface must be configured as eight data bits plus parity, 0.5 or 1.5 stop bits, with smartcard mode enabled. a 16-bit counter, the smartcard clock generator, divides down either the cpu clock, or an external clock connected to a pin shared with a pio bit, to provide the clock to the smartcard. pio bits in conjunction with software are used to provide the rest of the functions required to interface to the smartcard. the inverse signalling convention, as defined in iso7816-3, is handled in software, inverted data and most significant bit first. see asynchronous serial controller on page 253 for details of the asc and parallel input/output port on page 272 for details of the pio ports. 29.1 external interface the smartcard pin functions are described in the table below the scn_rst , scn_cmd_vcc , and scn_detect signals are provided by alternate functions of the pio pins. the uartn_txd data signal is connected to the scn_data pin with the correct driver type and the clock generator is connected to the scn_clk pin. the iso standard defines the bit times for the asynchronous protocol in etus, which are related to the clock frequency received by the card. one bit time = one etu. the asc transmitter output and receiver input must be connected together externally. for the transmission of data from the STI5518 to the smartcard, the asc must be set up in smartcard mode. pin in/out function scn_clk out, open drain for 5v cards clock for smartcard sc external clock in external clock input to smartcard clock divider scn_data out, open drain driver serial data output. open drain drive scn_data in serial data input scn_rst out, open drain reset to card scn_cmd_vcc out supply voltage enable/disable scn_detect in smartcard detection scn_data_dir out indicates if the smartcard is operating in serial data output (open drain drive) mode or serial data input mode. table 114 smartcard interface pins figure 179 iso 7816-3 asynchronous protocol line is pulled low by the receiver during stop bits if there is a parity error sa bcde f g hp start bit 8 data bits parity bit 11 etu
c o n f i d e n t i a l 29 smartcard interface STI5518 252/294 7170179 d 29.2 smartcard clock generator the smartcard clock generator provides a clock signal to the smartcard. the smartcard uses this clock to derive the baud-rate clock for the serial i/o between the smartcard and another uart. the clock is also used for the cpu in the card, if there is one present. operation of the smartcard interface requires that the clock rate to the card is adjusted while the cpu in the card is running code, so that the baud rate can be changed or the performance of the card can be increased. the protocols that govern the negotiation of these clock rates and the altering of the clock rate are detailed in the iso7816-3 standard. the clock is used as the cpu clock for the smartcard, so updates to the clock rate must be synchronized with the clock to the smartcard. this means the clock high or low pulse widths must not be shorter than either the old or new programmed value. the clock generator clock source can be set to the system clock or an external pin. two following two registers control the period of the clock and the running of the clock. the sci_n_clkval determines the smartcard clock frequency. the value given in the register is multiplied by 2 to give the division factor of the input clock frequency. the divider is updated with the new value for the divider ratio on the next rising or falling edge of the output clock. the desired, non zero, value must be programmed into register sci_n_clkval before the clocks are enabled (by setting the enable bit in register sci_n_clkcon.) the sci_n_clkcon controls the source of the clock and determines whether the smartcard clock output is enabled. the programmable divider and the output are reset when the enable bit is set to 0. figure 180 smartcard clock generation schematic smcard clock freq synthesizer pio1[2] external pad smcard_controller 5 5 scn_clock signal sci_n_clkcon[1] sci_n_clkcon sci_n_clkval[4:0] external clock signal st20 clock sci_n_clkcon[0] tpmac clock generator smartcard clock source domain enable divider divratio[4:0] c e d q sync d q
c o n f i d e n t i a l STI5518 30 asynchronous serial controller 7170179 d 253/294 30 asynchronous serial controller the asynchronous serial controller (asc), also referred to as the uart interface, provides serial communication between the STI5518 and other microcontrollers, microprocessors or external peripherals. the STI5518 provides four ascs, two of which are generally used by the smartcard controllers. eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. parity, framing, and overrun error detection is provided to increase the reliability of data transfers. transmission and reception of data can simply be double-buffered, or 16-deep fifos may be used. handshaking is supported on both transmission and reception. for multiprocessor communication, a mechanism to distinguish the address from the data bytes is included. testing is supported by a loop-back option. a dual mode 16-bit baud rate generator provides the asc with a separate serial clock signal. two ascs support full-duplex and 2 half-duplex asynchronous communication, where both the transmitter and the receiver use the same data frame format and the same baud rate. for the full-duplex ascs, data is transmitted on the transmit data output pin txd and received on the receive data input pin rxd. each asc can be set to operate in smartcard mode for use when interfacing to a smartcard. the registers for each asc are grouped in a 4 kbyte block, with the base of the block for asc number n at the address ascnbaseaddress . the value of each ascnbaseaddress is given in the STI5518 register manual . 30.1 control the asc_n_control register controls the operating mode of the asc. it contains control and enable bits, error check selection bits, and status flags for error identification. serial data transmission or reception is only possible when the baud rate generator run bit (run) is set to 1. when the run bit is set to 0, txd will be 1. setting the run bit to 0 will immediately freeze the state of the transmitter and receiver and should only be done when the asc is idle. note: programming the mode control field (mode) to one of the reserved combinations may result in unpredictable behavior. the asc can be set to use either double-buffering or a 16-deep fifo on transmission and reception. 30.1.1 resetting the fifos the ? registers ? asc_n_txreset and asc_n_rxreset have no actual storage associated with them. a write of any value to one of these registers resets the corresponding fifo. 30.1.2 transmission and reception serial data transmission or reception is only possible when the baud rate generator run bit (run) is set to 1. a handshaking protocol is supported on both transmission and reception, using cts and rts signals. a transmission is started by writing to the transmit buffer register asc_n_txbuffer. because data transmission is double-buffered or uses a fifo (selectable in the asc_n_control register), a new character may be written to the transmit buffer register before the transmission of the previous character is complete. this allows characters to be sent back-to-back without gaps. data reception is enabled by the receiver enable bit (rxenable) in the control register. after reception of a character has been completed, the received data and, if provided by the selected operating mode, the parity error bit, can be read from the receive buffer register asc_n_rxbuffer. reception of a second character may begin before the received character has been read out of the receive buffer register. the overrun error status flag (overrunerror) in the status register asc_n_status will be set when the receive buffer register has not been read by the time reception of a second character is complete. the previously received
c o n f i d e n t i a l 30 asynchronous serial controller STI5518 254/294 7170179 d character in the receive buffer is overwritten, and the asc_n_status register is updated to reflect the reception of the new character. the loop-back option (selected by the loopback bit) internally connects the output of the transmitter shift register to the input of the receiver shift register. this may be used to test serial communication routines at an early stage without having to provide an external network. 30.2 data frames data frames may be 8-bit or 9-bit, with or without parity and with or without a wake-up bit. the data frame type is selected by the setting of the mode bit field in the control register. the transmitted data frame consists of three basic elements: the start bit; the data field (8 or 9 bits, least significant bit (lsb) first, including a parity bit or wake-up bit, if selected); the stop bits (0.5, 1, 1.5 or 2 stop bits). 30.2.1 8-bit data frames figure 181 illustrates a 8-bit transmitted data frame. 8-bit frames may use of one of the following formats: eight data bits d0-7 (mode set to 001); seven data bits d0-6 plus an automatically generated parity bit (mode set to 011). parity may be odd or even, depending on the parityodd bit in the asc_n_control register. if the modulo 2 sum of the seven data bits is 1, then the even parity bit will be set and the odd parity bit will be cleared. in receive mode the parity error flag (parityerror) will be set if a wrong parity bit is received. the parity error flag is stored in the 8th bit (d7) of the asc_n_rxbuffer register.the parity error bit is set high if there is a parity error. 30.2.2 9-bit data frames figure 182 illustrates a 9-bit transmitted data frame. 9-bit data frames use of one of the following formats: nine data bits d0-8 ( mode set to 100); eight data bits d0-7 plus an automatically generated parity bit ( mode set to 111); eight data bits d0-7 plus a wake-up bit ( mode set to 101) figure 181 8-bit tx data frame format start bit d0 d1 d2 d3 d4 d5 d6 8th bit (lsb) 1st stop bit 2nd stop bit ? data bit ( d7 ) ? parity bit
c o n f i d e n t i a l STI5518 30 asynchronous serial controller 7170179 d 255/294 . figure 182 9-bit tx data frame format parity may be odd or even, depending on the parityodd bit in the asc_n_control register. if the modulo 2 sum of the eight data bits is 1, then the even parity bit will be set and the odd parity bit will be cleared. the parity error flag (parityerror) will be set if a wrong parity bit is received. the parity error flag is stored in the 9th bit (d8) of the asc_n_rxbuffer register. the parity error bit is set high if there is a parity error. in wake-up mode, received frames are only transferred to the receive buffer register if the ninth bit (the wake-up bit) is 1. if this bit is 0, no receive interrupt request will be activated and no data will be transferred. this feature may be used to control communication in multi-processor systems. when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the additional ninth bit is a 1 for an address byte and a 0 for a data byte, so no slave will be interrupted by a data byte. an address byte will interrupt all slaves (operating in 8-bit data plus wake-up bit mode), so each slave can examine the 8 least significant bits (lsbs) of the received character, which is the address. the addressed slave will switch to 9-bit data mode, which enables it to receive the data bytes that will be coming (with the wake-up bit cleared). the slaves that are not being addressed remain in 8-bit data plus wake-up bit mode, ignoring the data bytes which follow. 30.3 transmission transmission begins at the next baud rate clock tick, provided that the run bit is set and data has been loaded into the asc_n_txbuffer. if the ctsenable bit is set in the asc_n_control register then transmission only occurs when cts is high. the transmitter empty flag (txempty) indicates whether the output shift register is empty. it will be set at the beginning of the last data frame bit that is transmitted, i.e. during the first system clock cycle of the first stop bit shifted out of t he transmit shift register. the loop-back option (selected by the loopback bit of the asc_n_control register) internally connects the output of the transmitter shift register to the input of the receiver shift register. this may be used to test serial communication routines at an early stage without having to provide an external network. 30.3.1 transmission with fifos enabled the fifos are enabled by setting the fifoenable bit of the asc_n_control register. the output fifo is implemented as a 16-deep array of 9-bit vectors. values to be transmitted are written to the output fifo by writing to asc_n_txbuffer. the txfull bit of the asc_n_status register is set when the transmit fifo is considered full, i.e. when it contains 16 characters. further writes to asc_n_txbuffer will fail to overwrite the most recent entry in the output fifo. the txhalfempty bit of the asc_n_status register is set when the output fifo contains 8 or fewer characters. values are shifted out of the bottom of the output fifo into a 9-bit output shift register in order to be transmitted. if the transmitter is idle (i.e. the output shift register is empty) and something is written to the asc_n_txbuffer so that the start bit d0 d1 d2 d3 d4 d5 d6 9th bit (lsb) 1st stop bit 2nd stop bit ? data bit ( d8 ) ? parity bit d7 ? wake-up bit
c o n f i d e n t i a l 30 asynchronous serial controller STI5518 256/294 7170179 d output fifo becomes non-empty, the output shift register is immediately loaded from the output fifo and transmission of the data in the output shift register begins at the next baud rate tick. when the transmitter is just about to transmit the stop bits, and if the output fifo is non-empty, the output shift register will be immediately loaded from the output fifo, and the transmission of this new data will begin as soon as the current stop bit period is over (i.e. the next start bit will be transmitted immediately following the current stop bit period). if the output fifo is empty at this point, the output shift register will become empty. thus back-to-back transmission of data can take place. if the output fifo is empty at this point, the output shift register will become empty. writing anything to asc_n_txreset empties the output fifo. after changing the fifoenable bit, it is important to reset the fifo to empty (by writing to the asc_n_txreset register), or garbage may be transmitted. 30.3.2 double-buffered transmission double buffering is enabled and the fifos disabled by writing 0 to the fifoenable bit of the asc_n_control register. when the transmitter is idle, the transmit data written into the transmit buffer asc_n_txbuffer is immediately moved to the transmit shift register, thus freeing the transmit buffer for the next data to be sent. this is indicated by the transmi t buffer empty flag (txhalfempty) being set. the transmit buffer can be loaded with the next data while transmission of the previous data is still going on. when the fifos are disabled, the txfull bit is set when the buffer contains 1 character, and a write to asc_n_txbuffer in this situation will overwrite the contents. the txhalfempty bit of the asc_n_status register is set when the output buffer is empty. 30.4 reception reception is initiated by a falling edge on the data input pin rxd, provided that the run and rxenable bits of the asc_n_control register are set. controlled data transfer can be achieved using the rts handshaking signal provided by the uart. the sender checks the rts to ensure the uart is ready to receive data. in double-buffered reception rts goes high when asc_n_rxbuffer is empty, in fifo-controlled operation it goes high when rxhalffull is zero. the rxd pin is sampled at 16 times the rate of the selected baud rate. a majority decision of the first, second and third samples of the start bit determines the effective bit value. this avoids erroneous results that may be caused by noise. if the detected value of the first bit of a frame is not a 0, then the receive circuit is reset and waits for the next falling edge transition at the rxd pin. if the start bit is valid, i.e. is 0, the receive circuit continues sampling and shifts the incoming data frame into the receive shift register. for subsequent data and parity bits, the majority decision of the seventh, eighth and ninth samples in each bit time is used to determine the effective bit value. the effective values received on rxd are shifted into a 10-bit input shift register. for 0.5 stop bits, the majority decision of the third, fourth, and fifth samples during the stop bit is used to determine the effective stop bit value. for 1 and 2 stop bits, the majority decision of the seventh, eighth, and ninth samples during the stop bits is used to determine the effective stop bit values. for 1.5 stop bits, the majority decision of the fifteenth, sixteenth, and seventeenth samples during the stop bits is used to determine the effective stop bit value. reception is stopped by clearing the rxenable bit of asc_n_control. any currently received frame is completed including the generation of the receive status flags. start bits that follow this frame will not be recognized. 30.4.1 hardware error detection to improve the safety of serial data exchange, the asc provides three error status flags in the asc_n_status register which indicate if an error has been detected during reception of the last data frame and associated stop bits. the parity error bit (parityerror) in the asc_n_status register is set when the parity check on the received data is incorrect. in fifo operation parity errors on the buffers are or-ed to yield a single parity error bit.
c o n f i d e n t i a l STI5518 30 asynchronous serial controller 7170179 d 257/294 the framing error bit (frameerror) in the asc_n_status register is set when the rxd pin is not a 1 during the programmed number of stop bit times (see section 30.4). in fifo operation the bit remains set while at least one of the entries has a frame error. the overrun error bit (overrunerror) in the asc_n_status register is set when the input buffer is full and a character has not been read out of the asc_n_rxbuffer register before reception of a new frame is complete. these flags are updated simultaneously with the transfer of data to the receive input buffer. 30.4.1.1 frame and parity errors the most significant bit (bit 9 of 0-9) of each input entry records whether or not there was a frame error when that entry was received (i.e. one of the effective stop bit values was ? 0 ? ). the frameerror bit of the asc_n_status register is set when the input buffer (double-buffered operation), or at least one of the valid entries in the input buffering (fifo- controlled operation), has its most significant bit set. if the mode is one where a parity bit is expected, then the next bit (bit 8 of 0-9) records whether there was a parity error when that entry was received. it does not contain the parity bit that was received. for 7-bit+parity data frames the parity error bit is set in both the eighth (bit 7 of 0-9) and the ninth (bit 8 of 0-9) bits. the parityerror bit of asc_n_status is set when the input buffer (double-buffered operation), or at least one of the valid entries in the input buffering (fifo- controlled operation), has bit 8 set. when receiving 8-bit data frames without parity (see section 30.2.1), the ninth bit of each input entry (bit 8 of 0-9) is undefined. 30.4.2 input buffering modes 30.4.2.1 fifo enabled reception the fifos are enabled by setting the fifoenable bit of the asc_n_control register. the input fifo is implemented as a 16-deep array of 10-bit vectors (each 9 down to 0). if the input fifo is empty i.e. no entries are present, the rxbuffull bit of the asc_n_status register is set to ? 0 ? . if one or more fifo entries are present, the rxbuffull bit of the asc_n_status register is set to 1. if the input fifo is not empty, a read from asc_n_rxbuffer will get the oldest entry in the input fifo. the rxhalffull bit of the asc_n_status register is set when the input fifo contains more than 8 characters. writing anything to asc_n_rxreset empties the input fifo. as soon as the effective value of the last stop bit has been determined, the content of the input shift register is transferred to the input fifo (except during wake-up mode, in which case this happens only if the wake-up bit, bit 8, is a ? 1 ? ). the receive circuit then waits for the next falling edge transition at the rxd pin. the overrunerror bit of the asc_n_status register is set when the input fifo is full and a character is loaded from the input shift register into the input fifo. it is cleared when the asc_n_rxbuffer register is read. after changing the fifoenable bit, it is important to reset the fifo to empty by writing to the asc_n_rxr eset register; otherwise the state of the fifo pointers may be garbage. 30.4.2.2 double buffered reception double buffered operation is enabled and the fifos disabled by writing 0 to the fifoenable bit of the asc_n_control register. this mode can be seen as equivalent to a fifo-controlled operation with a fifo of length 1 (the first fifo vector is in fact used as the buffer). when the last stop bit has been received (at the end of the last programmed stop bit period) the content of the receive shift register is transferred to the receive data buffer register (asc_n_rxbuffer). the receive buffer full flag (rxbuffull) is set, and the parity (parityerror) and framing error (frameerror) flags are updated at the same time, after the last stop bit has been received, i.e. at the end of the last stop bit programmed period. the flags are updated even if no valid stop bits have been received. the receive circuit then waits for the next falling edge transition at the rxd pin.
c o n f i d e n t i a l 30 asynchronous serial controller STI5518 258/294 7170179 d 30.4.3 time-out mechanism the asc contains an 8-bit time-out counter. this reloads from asc_n_timeout whenever one or more of the following is true: asc_n_rxbuffer is read; the asc is in the middle of receiving a character; asc_n_timeout is written to. if none of these conditions hold the counter decrements towards 0 at every baud rate tick. the timeoutnotempty bit of the asc_n_status register is ? 1 ? when the input fifo is not empty and the time-out counter is zero. the timeoutidle bit of the asc_n_status register is ? 1 ? when the input fifo is empty and the time-out counter is zero. the effect of this is that whenever the input fifo has got something in it, the time-out counter will decrement until something happens to the input fifo. if nothing happens, and the time-out counter reaches zero, the timeoutnotempty bit of the asc_n_status register will be set. when the software has emptied the input fifo, the time-out counter will reset and start decrementing. if no more characters arrive, when the counter reaches zero the timeoutidle bit of the asc_n_status register will be set. 30.5 baud rate generation each asc has its own dedicated 16-bit baud rate generator with 16-bit reload capability. the baud rate generator has two possible modes of operation. the asc_n_baudrate register is the dual-function baud rate generator and reload value register. a read from this register returns the content of the counter or accumulator (depending on the mode of operation); writing to it updates the reload register. if the run bit of the control register is 1, then any value written in the asc_n_baudrate register is immediately copied to the counter/accumulator. however, if the run bit is 0 when the register is written, then the counter/ accumulator will not be reloaded until the first cpu clock cycle after the run bit is 1. the baud rate generator supports two modes of operation, offering a wide range of possible values. the mode is set via the baudmode bit in the asc_n_control register. mode 0 is a simple counter driven by the cpu clock whereas mode 1 uses a loop-back accumulator. mode 0 is recommended for low baud rates (below 19.2k baud), where its error deviation is low, and mode 1 is recommended for baud rates above 19.2 k. 30.5.1 baud rates the baud rate generator provides an internal oversampling clock at 16 times the external baud rate. this clock only ticks if the run bit of the asc_n_control register is set to 1. setting this bit to 0 will immediately freeze the state of the ascs transmitter and receiver.
c o n f i d e n t i a l STI5518 30 asynchronous serial controller 7170179 d 259/294 30.5.1.1 mode 0 when the baudmode bit in the asc_n_control register is set to 0, the baud rate and the required reload value for a given baud rate can be determined by the following formulae: where: ascbaudrate represents the content of the asc_n_baudrate reload value register, taken as an unsigned 16-bit integer and f cpu is the frequency of the cpu. the baud rate counter is clocked by the cpu clock. it counts downwards and can be started or stopped by the run bit in the asc_n_control register. each underflow of the timer provides one oversampling baud rate clock pulse. the counter is reloaded with the value stored in its 16-bit reload register each time it underflows. writes to the asc_n_baudrate register update the reload register value. reads from the asc_n_baudrate register return the current value of the counter. 30.5.1.2 mode 1 when the baudmode bit in the asc_n_control register is set to 1, the baud rate is controlled by the following circuit. writes to asc_n_baudrate go to the reload register. reads from asc_n_baudrate return the value in the accumulator register. both registers are 16 bit wide and are clocked by the cpu clock. if the system clock frequency is f cpu , writing a value of ascbaudrate to the asc_n_baudrate register results in an average oversampling clock frequency of: so the baud rate is given by: this gives good granularity, and hence low baud rate deviation errors, at high baud rate frequencies. figure 183 mode1 baudrate = 16 x ascbaudrate ascbaudrate = 16 x baudrate f cpu f cpu ascbaudrate carry-out oversampling clock (reload) ascbaudrate (accumulator) f cpu 2 16 ascbaudrate x f cpu baudrate = 16 x 2 16 ascbaudrate x f cpu
c o n f i d e n t i a l 30 asynchronous serial controller STI5518 260/294 7170179 d 30.6 interrupt control each asc contains two registers that are used to control interrupts, the status register (asc_n_status) and the interrupt enable register (asc_n_intenable). the status bits in the asc_n_status register show the cause of any interrupt. the interrupt enable register allows certain interrupt causes to be masked. interrupts will occur when a status bit is 1 (high) and the corresponding bit in the asc_n_intenable register is 1. the asc interrupt signal is generated from the or of all interrupt status bits after they have been anded with the corresponding enable bits in the asc_n_intenable register, as shown in figure 184 . the status bits cannot be reset by software because the asc_n_status register cannot be written to directly. status bits are reset by operations performed by the interrupt handler: transmitter interrupt status bits (txempty, txhalfempty) are reset when a character is written to the transmitter buffer. receiver interrupt status bit (rxbuffull) is reset when a character is read from the receive buffer. parityerror and frameerror status bits are reset when all characters containing errors have been read from the receive input buffer. the overrunerror status bit is reset when a character is read from asc_n_rxbuffer. 30.6.1 using the asc interrupts when fifos are disabled (double-buffered operation) the transmitter generates two interrupts; this provides advantages for the servicing software. for normal operation (i.e. other than the error interrupt) when fifos are disabled the asc provides three interrupt requests to control data exchange via the serial channel: txhalfempty is activated when data is moved from asc_n_txbuffer to the transmit shift register; txempty is activated before the last bit of a frame is transmitted;
c o n f i d e n t i a l STI5518 30 asynchronous serial controller 7170179 d 261/294 rxbuffull is activated when the received frame is moved to asc_n_rxbuffer. as shown in figure 185 ,txhalfempty is an early trigger for the reload routine, while txempty indicates the completed transmission of the data field of the frame. therefore, software using handshake should rely on txempty at the end of a data block to make sure that all data has really been transmitted. for single transfers it is sufficient to use the transmitter interrupt (txempty), which indicates that the previously loaded data has been transmitted, except for the last bit of a frame. for multiple back-to-back transfers it is necessary to load the next data before the last bit of the previous frame has been transmitted. the use of txempty alone would leave just one stop bit time for the handler to respond to the interrupt and initiate another transmission. using the output buffer interrupt (txhalfempty) to signal for more data allows the service routine to load a complete frame, as asc_n_txbuffer may be reloaded while the previous data is still being transmitted. 30.6.2 using the asc interrupts when fifos are enabled to transmit a large number of characters back to back, the driver routine would initially write 16 characters to asc_n_txbuffer. then every time a txhalfempty interrupt fired, it would write 8 more. when there is nothing more to send, a txempty interrupt would tell the driver that everything has been transmitted. when receiving, the driver could use rxbuffull to interrupt every time a character arrived. alternatively, if data is coming in back-to-back, it could use rxhalffull to interrupt it when there was more than 8 characters in the input fifo to read. it would have as long as it takes to receive 8 characters to respond to this interrupt before data could overrun. figure 184 asc status and interrupt registers and rxbuffullie txemptyie parityerrorie frameerrorie overrunerrorie rxbuffull parityerror frameerror overrunerror or asc interrupt and and and and and timeoutnotempty timeoutidle rxhalffull txfull and and and timeoutnotemptyie timeoutidleie rxhalffullie nacked txempty txhalfempty txhalfemptyie
c o n f i d e n t i a l 30 asynchronous serial controller STI5518 262/294 7170179 d if less than 8 characters streamed in, and no more were received for at least a time-out period, the driver could be woken up by one of the two time-out interrupts, timeoutnotempty or timeoutidle. 30.7 smartcard operation smartcard mode is selected by setting the scenable bit in the asc_n_control register to 1. in smartcard mode the rxd and txd ports of the uart are both connected externally via a single bidirectional line to a smart card io port. characters are transferred to and from the smart card as 8-bit data frames with parity (see section 30.2). handshaking between the uart and the smartcard ensures secure data transfer. when the scenable bit in the asc_n_control register is set to 0, normal uart operation occurs. smartcard operation complies win the iso smartcard specification except where noted (see section 30.7.4). 30.7.1 control registers asc_n_guardtime a programmable 8-bit register asc_n_guardtime controls the time between transmitting the parity bit of a character and the start bit of any further bytes, or transmitting a ? nack ? ( ? no acknowledge ? signal, see section 30.7.2.1). during the guardtime period the uart receiver is insensitive to possible start bits and the smart card is free to send ? nacks ? . figure 185 asc transmission figure 186 asc reception idle idle start start start stop stop stop txempty interrupt output shift register transmission asctxbuffer register char 2 char 1 char 2 char 3 char 3 char 1 char 2 char 3 write char1 write char2 write char3 txhalfempty interrupt idle idle start start start stop stop stop rxbuffull input shift register receive ascrxbuffer register char1 char 2 char 1 char 2 char 3 char 3 char 1 char 2 char 3
c o n f i d e n t i a l STI5518 30 asynchronous serial controller 7170179 d 263/294 guardtime should always be set to at least 2. asc_n_retries a programmable 8-bit register asc_n_retries defines the number of times the uart will automatically try to send a ? nacked ? character before giving up. 30.7.2 transmission in smartcard mode fifos can be either enabled or disabled. if fifos are disabled, the uart transmission behaves according to ndc requirements. 30.7.2.1 handshaking when the uart is transmitting data to the smart card, the smart card can ? nack ? ( ? not acknowledge ? ) the transmission by pulling the line low 0.5 baud clock period into the guardtime period and holding it low for at least 1 baud clock period. the uart should also be programmed in 1.5 stop bit mode, and since it receives what it transmits, nacks will be detected as receive framing errors. 30.7.2.2 behavior with fifos enabled at about 1 baud clock period into the guardtime period, the uart knows whether or not the transmitted character has been ? nacked ? . if no nack has been received and the tx fifo is not empty, the next character is transmitted after the guardtime period. if a transmitted character is nacked by the receiving uart, the character is retransmitted as soon as the guardtime period expires (or if guardtime is 2, an extra baud clock period later), and retransmission is attempted up to the number of retries set in the asc_n_retries register. if the last retry is also ? nacked ? the tx fifo is emptied, putting the transmitter into an idle state, and the nacked bit is set in the asc_n_status register. emptying of the fifo causes an interrupt, which can be handled by software. the nacked bit in the asc_n_status register can be reset by writing to the asc_n_txr eset register. all ? un-nacked ? (successfully transmitted) data is looped-back into the receive fifo. this fifo can be read by software to determine the status of the data transmission. 30.7.2.3 behavior with fifos disabled when the smartcard mode bit is set to 1, the following operation occurs. transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of 1/2 baud clock. in normal operation a full transmit shift register will start shifting on the next baud clock edge. in smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. if a parity error is detected during reception of a frame programmed with a 1/2 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame, i.e. at the end of the 1/2 stop bit period. this is to indicate to the smartcard that the data transmitted to the uart has not been correctly received. the assertion of the txempty interrupt can be delayed by programming the asc_n_guardtime register. in normal operation, txempty is asserted when the transmit shift register is empty and no further transmit requests are outstanding. the receiver enable bit in the control register is automatically reset after a character has been transmitted. this avoids the receiver detecting a ? nack ? from the smartcard as a start bit. in smartcard mode an empty transmit shift register triggers the guardtime counter to count up to the programmed value in the asc_n_guardtime register. txempty is forced low during this time. when the guard time counter reaches the programmed value txempty is asserted high.
c o n f i d e n t i a l 30 asynchronous serial controller STI5518 264/294 7170179 d the de-assertion of txempty is unaffected by smartcard mode. 30.7.3 reception reception can be done with fifos either enabled or disabled. the behavior is the same as in normal (non-smartcard) mode except that if a parity error occurs, then providing the transmitter is idle, the uart will transmit a nack on the txd for 1 etu from the end of the received stop bit. rxd is masked when transmitting a nack, since txd is tied to rxd and a nack must not be seen as a start bit. 30.7.4 divergence from iso smartcard specification this uart does not support guardtimes of 0 or 1, and does not have any special behavior for a guardtime of 255.
c o n f i d e n t i a l STI5518 31 synchronous serial controller 7170179 d 265/294 31 synchronous serial controller 31.1 introduction the high-speed synchronous serial controller (ssc) interfaces to a wide variety of serial memories, remote control receivers, and other microcontrollers. several interface standards can be used including the i 2 c bus in the set-top box application. the figure below shows how the ssc is interfaced to an i 2 c bus as the bus master. software or hardware handles the i 2 c bus protocol such as byte acknowledgment, see section 31.9: i2c hardware configuration on page 271. the ssc provides flexible high-speed serial communication between the STI5518 and other microprocessors or external peripherals, using the i 2 c bus protocol, as a master or slave. the ssc supports half-duplex synchronous communication. the serial clock signal can be generated by the ssc itself in master mode, and data width is programmable. transmission and reception of data is double-buffered. a 16-bit baud rate generator provides the ssc with a separate serial clock signal. the high-speed synchronous serial controller can be used to communicate with shift registers (i/o expansion), peripherals (e.g. eeproms) or other controllers (networking). the ssc supports half-duplex communication. figure 187 ssc interface to i 2 c bus mtsr / mrst sclk vdd a0 vss(gnd) a1 a2 sda scl vdd gnd 10nf 2.7k 2.7k st24c02 slave STI5518 master
c o n f i d e n t i a l 31 synchronous serial controller STI5518 266/294 7170179 d 31.2 synchronous serial channel operation the ssc shift register is connected to both the transmit pin and the receive pin via the pin control logic. this is illustrated in the block diagram above. transmission and reception of serial data is synchronized and the same number of bits are transmitted as received. transmit data is written into the transmit buffer (ssc_n_txbuf) register, and moved to the shift register as soon as the shift register is empty. then it is transmitted via the ssc. when the data has transferred to the shift register, the transmit buffer empty (txbufempty) flag is set to indicate that the transmit buffer may be reloaded. when the programmed number of bits (from 2 to 16) has been transferred, the contents of the shift register are moved to the receive buffer (ssc_n_rbuf) register and the receive buffer full (rxbuffull) flag is set. if no further transfer is to take place, i.e. the transmit buffer is empty, the ssc reverts back to an idle state, waiting for a load of the transmit register. note only one ssc can be master at a given time. the serial data bits can be transferred with data width from 2 to 16 bits (set by register bit ssc_n_con.bm) and for a wide range of baud rates (set by register ssc_n_brg). unused bits of registers ssc_n_tbuf and ssc_n_rbuf must be ignored. figure 188 synchronous serial channel block diagram receiver buffer transmitter empty receive error or gate full interrupt interrupt interrupt phase error interrupt cpu clock baud rate generator clock control slave clock master clock shift clock ssc control block ssc interrupt status control 16-bit shift register pin control transmit buffer reg ( ssc_n_tbuf ) receive buffer reg ( ssc_n_rbuf ) internal bus sclk mtsr mrst
c o n f i d e n t i a l STI5518 31 synchronous serial controller 7170179 d 267/294 31.3 ssc clocking when ssc_n_con register bits clkphase=0 and clkpolarity=0, then the clock and data relationship are i 2 c compatible. the data is stable during the high level of the clock, and i 2 c setup and hold times are met. this is illustrated in the figure below. figure 189 clock and data relationships clkpolarity clkphase 0 0 transmit data last bit latch data shift data first bit serial clock sclk pins mtsr / mrst
c o n f i d e n t i a l 31 synchronous serial controller STI5518 268/294 7170179 d 31.4 half-duplex operation in a half duplex configuration, only one data line is necessary for both the reception and transmission of data. the data exchange line is connected to both pins mtsr and mrst of each device, the clock line is connected to the sclk pin. the master device controls data transfer by generating the shift clock, while the slave devices receive it. due to the fact that all transmit and receive pins are connected to the one data exchange line, serial data may be moved between arbitrary stations. similar to full duplex mode, there are two ways to avoid collisions on the data exchange line: only the transmitting device may enable its transmit pin driver the non-transmitting devices use open drain output and only send ones. since the data inputs and outputs are connected together, a transmitting device clocks its own data at the input pin (mrst for a master device). this allows detection of any corruptions on the common data exchange line, where the received data is not equal to the transmitted data. 31.5 continuous transfers when the register bit ssc_n_stat.tir=1, the transmit buffer ssc_n_tbuf is empty and ready to be loaded with the next transmit data. if ssc_n_tbuf has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the next transmission starts without any delay. on the data line there is no gap between the two successive frames. for example, two byte transfers would look the same as one word transfer. this feature can be used to interface with devices which can operate with, or require more than, 16 data bits per transfer. software determines how long a total data frame length can be. this option can also be used to interface to figure 190 half-duplex configuration master device #1 slave device #2 slave device #3 clock mtsr mrst sclk clock shift register mtsr mrst sclk clock shift register common transmit / receive line mtsr mrst sclk shift register clock
c o n f i d e n t i a l STI5518 31 synchronous serial controller 7170179 d 269/294 byte-wide and word-wide devices on the same serial bus. note that this can only happen in multiples of the selected basic data width, since it would require disabling/enabling of the ssc to reprogram the basic data width on-the-fly. 31.6 baud rates the ssc has its own dedicated 16-bit baud rate generator with 16-bit reload capability. the resultant baud rate for transmission and reception is half the value in the ssc_n_brg register. the formulae below calculate either the resulting baud rate for a given reload value, or the required reload value for a given baud rate: where, represents the content of the reload register as an unsigned 16-bit integer, and f cpu represents the cpu clock frequency. the maximum baud rate that can be achieved with a cpu clock of 40 mhz is 5 mbaud. the table below lists some possible baud rates, together with the required reload values and the resulting bit times, assuming a cpu clock of 40 mhz. 31.7 hardware error detection capabilities the ssc can detect two different error conditions. receive error phase error when an error is detected, the respective error flag is set in the scc_n_status register. the error interrupt handler can then check the error flags to determine the cause of the error interrupt. a receive error is detected, when a new data frame is completely received, but the previous data was not read out of the receive buffer register ssc_n_rbuf. this condition sets the error (rxerror) flag and, when enabled via rxerrorie, the error interrupt request flag (errorinterrupt). the old data in the receive buffer ssc_n_rbuf will be overwritten with the new value and is irretrievably lost. baud rate bit time reload value reserved. use a reload value > 0 - #0000 5 mbaud 200 ns #0004 3.3 mbaud 300 ns #0006 2.5 mbaud 400 ns #0008 2.0 mbaud 500 ns #000a 1.0 mbaud 1 s #0014 100 kbaud 10 s #00c8 10 kbaud 100 s #07d0 1.0 kbaud 1 ms #4e20 table 115 baud rates and bit times for different ssc_n_brg reload values baudrate 2 x = ( 2 x baudrate ) = f cpu f cpu
c o n f i d e n t i a l 31 synchronous serial controller STI5518 270/294 7170179 d a phase error is detected, when the incoming data on the mrst pin, sampled at the same frequency as the cpu clock, changes between one sample before and two samples after the latching edge of the clock signal. this condition sets the error flag phaseerror and, when enabled via phaseerrorie, the error interrupt request flag (errorinterrupt). 31.8 interrupt control the ssc has two registers to control interrupts, a status (ssc_n_status) register and an interrupt enable (ssc_n_ien) register. the status bits in the ssc_n_status register determine the cause of the interrupt. interrupts occur when a status bit =1 and the corresponding bit in the ssc_n_ien register=1. the error interrupt signal (errorinterrupt) is generated by the ssc from the or of the receive error and phase error status bits after they have been anded with the corresponding enable bits in the ssc_n_ien register. an overall interrupt request signal (sscinterrupt) is generated from the or of the receive interrupt request (rxbuffull), transmit interrupt request (txbufempty) and error interrupt request (errorinterrupt) signals. the status register cannot be written to directly by software. the set and reset mechanism for the status register is described below. the receiver interrupt status bit (rxbuffull) is set when a character is loaded from the shift register into the receive buffer (sscrxbuffer). the rxbuffull bit is reset when a character is read from the receive buffer (sscrxbuffer). the transmitter interrupt status bit (txbufempty) is set when a character is loaded from the transmitter buffer (ssctxbuffer) into the shift register. the txbufempty bit is reset when a character is written into the transmitter buffer (ssctxbuffer). the status bits (rxerror, phaseerror) are reset when a character is read from the receive buffer (sscrxbuffer). an interrupt handler for the ssc must read the scc_n_status register before writing the scc_n_tbuf or reading the scc_n_rbuf, as there might have been an error. the error flags are cleared by these read or write operations. figure 191 ssc status and interrupt registers & & & & ssc_n_status register register ssc_n_ien rxbuffullie txbufemptyie rxerrorie phaseerrorie rxbuffull txbufempty rxerror phaseerror receiver buffer full interrupt transmitter buffer empty interrupt reserved read 0, write 0 reserved read 0, write 0 reserved read 0, write 0 reserved read 0, write 0 receive error interrupt phase error interrupt
c o n f i d e n t i a l STI5518 31 synchronous serial controller 7170179 d 271/294 31.9 i 2 c hardware configuration in order to reduce the load on the cpu, the hardware configuration of the i 2 c interface can be used. this is selected by setting register.bit ssc_n_i2c.i2cm=1. in this configuration, start, stop and acknowledge are handled automatically by the hardware. when bit i2cm=1, register ssc_n_i2c is used in the following way: to generate a start condition set bit strtg=1 and then load register ssc_n_tbuf with the data to be transmitted; transmission begins automatically when this register is loaded. you must reset strtg after the device address is sent to generate a stop condition in order to terminate the transmission, set bit stopg=1. reset stopg after the stop condition is sent. to generate an acknowledge set ackg=1.
c o n f i d e n t i a l 32 parallel input/output port STI5518 272/294 7170179 d 32 parallel input/output port 44 bits of parallel i/o are configured in 6 ports, and each bit is programmable as output or input. the output can be configured as a totem-pole or open-drain driver. the input compare logic can generate an interrupt on any change of any input bit. many parallel io have alternate functions and can be connected to an internal peripheral signal such as a uart or ssc. the pio ports can be controlled by registers, mapped into the device address space. the registers for each port are grouped in a 4 kbyte block, with the base of the block for port n at the address pionbaseaddress . during reset all of the registers are reset to zero. each eight-bit pio port has a set of eight-bit registers. each of the eight bits of each register refers to the corresponding pin in the corresponding port. these registers hold: the output data for the port (pio_pnout). the input data read from the pin (pio_pnin). pio bit configuration registers (pio_pnc0-2). the two input compare function registers (pio_pncomp and pio_pnmask). each of the registers, except pio_pnin, is mapped onto two additional addresses so that bits can be set or cleared individually. pio_set_ registers set bits individually; writing a ? 1 ? in these registers sets a corresponding bit in an associated register, a ? 0 ? leaves the bit unchanged. pio_clear_ registers clear bits individually; writing a ? 1 ? in these registers resets a corresponding bit in an associated register, a ? 0 ? leaves the bit unchanged. the pio5[3] input is inversed for the pio and uhf input functions, but not inverted for the sdav functions.
c o n f i d e n t i a l STI5518 33 modem analog front-end interface 7170179 d 273/294 33 modem analog front-end interface 33.1 overview modem analog front-end interface (mafeif) is an integrated interface to a modem analog front end (afe) such as the stlc7550. in this chapter, the term ? sample ? is a 16-bit data-object that is transferred to or from the modem through the mafeif, and the term ? sample period ? is the time from the start of one sample to the start of the next. the mafeif simultaneously transmits samples into and out of the afe. it typically operates at a rate of 9600 samples/ second, giving a typical sample period of 100s. that is, every 100s, one sample is transmitted and another received through the mafeif. the mafeif receives its system clock signal (sclk) from the afe. the sclk frequency is typically 256 ticks/sample period, or 2.56 mhz. the first 16 ticks of the 256 tick sample period are used to exchange a 16-bit sample pair (1 bit per tick). the mafeif uses one dma to transfer samples from a transmit memory buffer to the afe, and simultaneously uses a second dma to receive samples from the afe and write them into the receive memory buffer. the software driver is ? woken-up ? every time a simultaneous transfer is completed - that is, every time a transmit memory buffer has been emptied and a receive memory buffer has been filled. for example, if each memory buffer contains 100 samples, the software is ? woken up ? every (100 x 100s) 10ms. this is more stringent for handshake signals where the buffer-size could be as low as a few samples, e.g. 4. the software modem has two pairs of pointers (i.e. four pointers) that point to two pairs of transmit/receive buffers. the modem and the mafeif alternately switch between the two pairs of pointers. while the mafeif transmits and receives using one pair of buffers, the software modem processes the information in the other pair. using the above example for a buffer containing 100 samples, the software has 10ms to wake-up and then process one pair of transmit/receive buffers before they are required again by the mafeif. 33.2 using the mafeif to connect to a modem the following table lists the pins that are by the mafeif to connect a modem: name pin # type mafeif function name (alt) mafeif function description pio2[1] 205 o mafeif_dout/para_req line for serially transmitting samples to the afe. pio2[2] 206 o mafeif_hc1 indicates to the afe that a control/status exchange will take place. pio3[0] 6 i mafeif_sclk/ para_data{0] modem system clock. the frequency should be less than half of the device system clock pio3[1] 7 i mafeif_din/para_data[1] line for serially receiving samples from the afe. pio3[2] 8 i mafeif_fsi/para_data[2] signal from the afe indicating the start of a sampling period. this is latched on fa lling edges of sclk. for normal operation it should not remain high for more than 16 sclk cycles, and there should be at least 20 sclk ticks between consecutive rising edges of fs. table 116 mafeif pins
c o n f i d e n t i a l 33 modem analog front-end interface STI5518 274/294 7170179 d 33.3 software the mafeif software manages the data exchange between the software modem and mafeif, and handles the control/status exchange. 33.3.1 data exchange when the mafeif exchanges data, the software: 1 disables all interrupts; 2 sets the buffer size, e.g. 100 samples; (for handshake response times, the buffer-size could be as low as a few samples, e.g. 4.) 3 sets-up both pairs of memory pointers in the mafeif (this will probably not be changed again); 4 enables status (complete) interrupt; 5 sets the control (run) bit; 6 deschedules. the mafeif then processes a buffer-load of samples (that is, it transmits 100 samples and receives 100 samples). when this is complete, the mafeif sets the status (complete) bit, causing the software to be ? woken-up ? . the software then continues as follows: 7 processes the receive memory buffer and fills the next transmit memory; 8 confirms that there has been no overflow (i.e. failure to finish the software processing of a buffer before that buffer has started to be overwritten again); 9 confirms that there have been no memory latency problems during the exchange of the previous buffer, by reading the status(missed) bit; 10 if everything is ok, sw writes to the acknowledge register and deschedules. 33.3.2 control/status exchange for a control/status exchange, the software writes to the mod_control register to enable the status interrupt (ctrl_empty), and then deschedules. when the software ? wakes-up ? , it reads the modem status and disables the status interrupt (ctrl_empty) again.
c o n f i d e n t i a l STI5518 34 infrared transmitter/receiver 7170179 d 275/294 34 infrared transmitter/receiver 34.1 introduction the ir transmitter/receiver is an st20 peripheral. for each symbol transmitted, the sw driver determines the symbol period and the symbol on-time of the ir pulse, and transfers these parameters into a 4-word deep fifo. the ir transmitter/receiver then generates coded symbols using an internally generated subcarrier clock. the parameters symbol period and symbol on-time are illustrated in the figure below. the incoming signal must be detected, and the subcarrier must be suppressed, externally. only the symbol envelope can be used by the ir and uhf processors. it is sampled at 10 mhz and the sample values are transferred into the input buffer in microseconds. 34.2 functional description overview the ir transmitter/receiver transmits infrared(ir)-data and receives both ir- and uhf-data. the ir and uhf receivers are independent and identical, except that the ir receiver does not use the noise filter. both receivers are simultaneously active. the ir transmitter/receiver supports rc (remote control) codes only. figure 193 shows the ir transmitter/receiver block diagram in a typical circuit configuration with input demodulating and output buffering (open drain). in the transmitter there are two programmable dividers to generate the prescaled clock and the subcarrier clock. the subcarrier clock sets the resolution for the transmitted data. both receivers contain a sampling-rate clock, which samples the incoming data, and is programmed to 10 mhz. fifos buffer both the transmitter output and the receivers ? inputs to avoid timing problems with the cpu. interrupts can be set on the fifos ? levels to prevent input data overrun and output data under-run. the two receivers each have one input pin, and the transmitter has two output pins (one driven directly and the other inverted as open drain). there are two 4-word fifos in the rc transmitter and two in each rc receiver. the fourth element in each 4-word fifos is used internally and is not accessible to the st-20 bus. therefore, the 4-word fifo is empty when there are three empty words and full when it contains three words. at all times, the fullness level of the 4-word fifo is given in the corresponding status register, as described later. the fifo pair, ? symbol period ? and ? symbol on-time ? , in each sub-module must be treated as a set and must be consecutively accessed for read or for write. they share a common pointer which is incremented only when they have figure 192 ir transmitter/receiver symbol symbol on-time symbol period
c o n f i d e n t i a l 34 infrared transmitter/receiver STI5518 276/294 7170179 d been accessed correctly. repeated reads on one fifo will always give the same data, and repeated writes will always over-write the previous data. rc transmit code processor rc codes are generated by programming the transmit frequency and writing the symbol information into a fifo. the fifo is then read internally and the data processed to provide a serial pwm data stream. the transmit interrupt is set on a pre-selected fifo level. an interrupt and a flag in the status register indicate an under-run condition (i.e. an empty fifo). rc data transmission is disabled by setting bit 0 of register ? irb_tx_en_ir to ? 0 ? . the transmit interrupt is set by register irb_tx_int_en_ir, on one of three fifo levels: when three words are empty (buffer is empty); when two or more words are empty (buffer is half full); when at least one word is empty. the transmit interrupt is cleared automatically when new data is written to the registers irb_tx_sym_period_ir and irb_tx_on_time_ir. register bits irb_tx_int_status_ir[5:4] give the fifo ? s fullness status. the frequency of the sub-carrier is set by programming the registers ? irb_tx_pre_scaler_ir and ? irb_tx_sub_carrier_ir ? . the symbol period, in sub-carrier cycles, is programmed in the register irb_tx_sym_period_ir and the on-time of the ir pulse is written to the register ? irb_tx_on_time_ir. these two registers are four-word fifos. they must be programmed sequentially as a pair to increment the write-pointer and be ready for the next data. transmission is enabled by setting register ? irb_tx_en_ir bit 0 to ? 1 ? . if new data is not written before the last symbol in the buffer is transmitted, no rc codes are generated. the output is driven to logic ? 0 ? and the register irb_tx_int_status_ir bit 1 is set. before data can be transmitted, the under-run condition must be cleared as follows: disable the transmission by writing ? 0 ? to register irb_tx_en_ir. figure 193 ir transmitter/receiver block diagram and implementation rc receive code processor uhf processor ir data out ir data in st20 bus pio5[3] pio5[4] pio5[5] pio5[2] rc transmit processor rc receive code processor ir processor code note: pio5[5] must be programmed in open drain mode ir module demod and carrier suppress uhf data in demod and carrier suppress input signal input signal
c o n f i d e n t i a l STI5518 34 infrared transmitter/receiver 7170179 d 277/294 load at least one block of data into irb_tx_sym_period_ir and irb_tx_on_time_ir. clear the ? tx_underrun ? status bit by writing ? 1 ? to register irb_tx_clr_underrun_ir transmission is resumed by writing ? 1 ? to register irb_tx_en_ir. rc receive code processor this section describes the uhf-data and the ir-data receivers. they are independent and identical except that the noise suppression filter is programmable in the uhf receiver, and is not used in the ir receiver. the 10 mhz sampling clock is common to both receivers and is set by register irb_rx_sampling_rate_common. this register is programmed with the value 5 for a 50 mhz irb system clock, or with the value 6 for a 60 mhz clock. each receiver processes the incoming rc code symbol envelope and stores the values ? symbol period ? and ? symbol on-time ? (in microseconds) in a four-word fifo buffer, until the data can be read by the microcontroller. the receive interrupt is set by register irb_rx_int_en to one of the following three fifo levels: at least one word is available to be read; two or more words or more are available to be read (fifo half full); three words are available to be read (fifo full). the interrupt is cleared automatically when the registers irb_rx_sym_period and irb_rx_on_time have been read. they must be read consecutively, as a pair, to increment the fifo read pointer. the register irb_rx_int_status bits 4 and 5 give the fullness level of the fifo. if the fifo is full and has not been read before the arrival of new data, then this data is lost and a receive overrun flag is set in the status register irb_rx_int_status. no new data is written to the fifo while this condition exists. to reset the overrun flag the following operations must be performed: read at least one word from each of the receive fifo registers, irb_rx_sym_period and irb_rx_on_time. clear the rxoverrunstatus bit by writing 0x01 to register irb_rx_clr_overrun. the last symbol is detected using a time-out condition whose value is stored in microseconds in register irb_rx_max_sym_period. if no pulse has been received during this time then the last word in the fifo irb_rx_sym_period has a value 0xffff. if the value of register irb_rx_int_en bit 1 (lastsymbolirqenable bit), is ? 1 ? , then an interrupt is triggered and the status register irb_rx_int_status bit 1 is set. the interrupt and its status bit are cleared automatically when the last value in the fifo has been read. when register irb_rx_int_en bit 0 is set to ? 0 ? then both the fifo level interrupt and the last symbol interrupt are inhibited. rc data reception can be disabled by setting register irb_rx_en bit 0 to ? 0 ? . however, both receivers are normally always enabled. noise suppression filter this filter is turned off in the ir receiver and is programmable in the uhf receiver using register irb_rx_noise_suppress_width_uhf. any pulses, either high or low, having a value in microsec onds of less than the programmed width, are assumed to be noise and, therefore, suppressed. the noise suppression filter can be disabled by writing ? 0x00 ? to register irb_rx_noise_suppress_width_uhf.
c o n f i d e n t i a l 35 electrical specifications STI5518 278/294 7170179 d 35 electrical specifications 35.1 absolute maximum ratings maximum limits indicate where permanent device damage occurs. continuous operation at these limits is not intended and should be limited to those conditions specified in dc electrical characteristics . 35.2 dc electrical characteristics 35.2.1 static operating conditions: vdd3_3 = 3.3v ! 0.3v, vdd2_5 = 2.5v ! 0.25v, t amb = 0 to 70 o c unless otherwise specified. symbol parameter min. max. units vdd3_3 power supply (pads) -0.5 4 v vdd2_5 power supply (core) -0.5 3 v vdd_rgb, vdd_ycc, vdd_pll, vdd_pcm power supply -0.5 4 v vi, vo voltage on input and output pins -0.5 4 v t stg storage temperature -65 +150 o c t oper ambient operating temperature 0 +70 o c table 117 absolute maximum ratings symbol parameter test conditions min. typ. max. units notes vdd3_3 operating voltage 3.0 3.3 3.6 v vdd2_5 operating voltage 2.25 2.5 2.75 v v il input logic low voltage -0.3 +0.8 v v ih input logic high voltage 2.0 3.6 v i i i oz input leakage current inputs outputs -10 -10 +10 +10 a a v ol output logic low voltage 0.4 v v oh output logic high voltage 2.4 v c in input capacitance 10 pf i dda analog current consumption r i_ref = 16.9k ? , r l = 200 ? 20 50 ma 10-bits d/a converter r i_ref resistance for reference current source for 3 d/a converters i _ref = v i_ref /r i_ref 16.9 k ? v o output voltage dyn r i_ref = 16.9 k ?, r l = 274 ? , vdd2_5 = 2.5v 1.21 1.31 1.41 v pp dac to dac v o max code (tri-dac only) r i_ref = 16.9 k ?, r l = 274 ? , vdd2_5 = 2.5v -5 +5 % iout dac output current 5.0 ma vout dac output voltage 1.45 v table 118 dc electrical characteristics
c o n f i d e n t i a l STI5518 35 electrical specifications 7170179 d 279/294 35.2.2 st20 running at 60.75 mhz 35.2.3 st20 running at 81.0 mhz ile lf integral non-linearity r i_ref = 16.9 k ?, r l = 274 ? , vdd2_5 = 2.5v -2 +2 lsbs dle lf differential non-linearity r i_ref = 16.9 k ?, r l = 274 ? , vdd2_5 = 2.5v -1 +1 lsbs symbol parameter test conditions min. typ. max. units notes vdd3_3 operating voltage 3.0 3.3 3.6 v vdd2_5 operating voltage 2.25 2.5 2.75 v idd3_3 average power supply current st20 operating frequency 60.75 mhz 60 150 ma idd2_5 average power supply current st20 operating frequency 60.75 mhz 650 750 ma 1 1. this figure includes the analogue current consumption. table 119 current consumption with st20 running at 60.75 mhz symbol parameter test conditions min. typ. max. units notes vdd3_3 operating voltage 3.15 3.3 3.45 v vdd2_5 operating voltage 2.35 2.5 2.65 v idd3_3 average power supply current st20 operating frequency 81.0 mhz, vdd3_3 = 3.3v ! 0.15v, vdd2_5 = 2.5v ! 0.15v 60 150 ma idd2_5 average power supply current st20 operating frequency 81.0 mhz, vdd3_3 = 3.3v ! 0.15v, vdd2_5 = 2.5v ! 0.15v 710 800 ma 1 1. this figure includes the analogue current consumption. table 120 current consumption with st20 running at 81.0 mhz symbol parameter test conditions min. typ. max. units notes table 118 dc electrical characteristics
c o n f i d e n t i a l 35 electrical specifications STI5518 280/294 7170179 d 35.3 ac test conditions test conditions: v dd 3_3 = 3.3v ! 0.3v, t amb = 0 to 70 o c, unless otherwise specified. 35.4 operating conditions figure 194 ac test conditions symbol parameter min. typ. max. units notes c ld load capacitance per smi pin (address, data and control) 15 pf c la load capacitance per emi pin (address, data and control) 30 pf c lp load capacitance per pio pin 30 pf table 121 operating conditions 1.4v 50 10pf output ac test conditions (50 ? adapted) z = 50
c o n f i d e n t i a l STI5518 35 electrical specifications 7170179 d 281/294 35.5 timing diagrams for io interfaces timings, other than rise and fall times, are specified with respect to a threshold of 1.5v. 35.5.1 input clock figure 195 input clock timing definitions symbol parameter min. typ. max. unit notes t pix_clk clock period (typically 27 mhz) 37.0 ns t high clock high time 16.5 18.5 20.5 ns t low clock low time 16.5 18.5 20.5 ns t r /t f clock rise/fall time 1.0 5.0 ns table 122 input clock timing values t r t f 2.0v 0.8v 2.0v 0.8v t high t low t pix_clk
c o n f i d e n t i a l 35 electrical specifications STI5518 282/294 7170179 d 35.5.2 smi interface when the smi interface is reading, the reference clock is smi_clkin (rising edge), and when it is writing, the reference is smi_clkout (falling edge). figure 196 ac parameters of read & write (synchronous dram) timing definitions symbol parameter min. typ. max. units notes t r_smi smi_clkout rise time 2 ns 1 t f_smi smi_clkout fall time 2 ns 1 t ck clock cycle time 7 ns t s data input setup time 2 ns t h data input hold time 2 ns t ac output data access time 2.1 ns 2 t oh output data hold time -3.1 ns 2 t sa address output delay time 2.1 ns 2 t ha address output hold time -3.1 ns 2 t cms command (cs , ras , cas , we , dqm) delay time 2.1 ns 2 t cmh command (cs , ras , cas , we , dqm) hold time -3.1 ns 2 t rcd delay time active to read/write command 4 t t rc ref to ref / active command period 8 t table 123 smi interface timing values smi_clkout t oh t ac output data address t ha t sa commands t cmh t cms smi_clkin t s t h input data delay t f_smi t r_smi (read) (write) (to sdram) (from sdram)
c o n f i d e n t i a l STI5518 35 electrical specifications 7170179 d 283/294 t rp active to pre command period 3 t t rrd active(a) to active(b) command period 4 t t dal data out to active command period 5 t t dpl data out to precharge command period 2 t t ras active to precharge command period 9 t 1. test conditions: c load = 10pf, 50 ? adapted mode at 1.4v, edge measured at 20%-80%. 2. negative values indicate that the timing is "before" the falling edge of smi_clkout. the output parameter definitions in figure 196 , are relative to the falling edge of smi_clkout. care must, therefore, be taken when interpreting the sdram data sheet which might have timings relative to the clock rising edge. figure 197 synchronous dram power-on sequence timing definitions symbol parameter min. typ. max. units notes table 123 smi interface timing values 4 cycles min. 4 cycles min. smi_we hi-z mode register data t rc t rc t rp all banks precharge command mode register write command cbr refresh cbr refresh activate command x32 smi_clkin/out smi_cs [0,1] smi_ras smi_cas smi_adr [11] smi_adr [10] smi_adr [0:9] smi_dqml, smi_dqml smi_dq [0:15] note, the number of refreshes required varies for different suppliers.
c o n f i d e n t i a l 35 electrical specifications STI5518 284/294 7170179 d figure 198 synchronous dram write burst (burst length = 4 cas latency = 3) timing definitions figure 199 synchronous dram read (burst length = 4 cas latency = 3) timing definitions write a active b precharge all t rrd t rp write b t dal t dpl t cmh t cms active a active b t rcd t rc smi_clkin/out smi_we smi_cs [0,1] smi_ras smi_cas smi_adr [11] smi_adr [10] smi_adr [0:9] smi_dqml, smi_dqml smi_dq [0:15] read b read a precharge all t rp t cmh t cms active a active a t rcd t ras t rc smi_clkin/out smi_we smi_cs [0,1] smi_ras smi_cas smi_adr [11] smi_adr [10] smi_adr [0:9] smi_dqml, smi_dqml smi_dq [0:15]
c o n f i d e n t i a l STI5518 35 electrical specifications 7170179 d 285/294 35.5.3 video interface the video timings given in the table below are referenced to the rising edge (unless otherwise indicated) of the external clock pix_clk. symbol parameter min. typ. max. units notes t syckenot0 oddeven setup time 4.0 ns t sycksync hsync setup time 4.0 ns t cksyenot0 oddeven hold time 4.0 ns t cksysync hsync hold time 4.0 ns t ckpv yc7-yc0 output delay time 15 ns table 124 video interface timing values figure 200 video interface timing definitions t ckpv yc7-yc0 (outputs) pix_clk t cksy hsync oddeven (inputs) t syck
c o n f i d e n t i a l 35 electrical specifications STI5518 286/294 7170179 d 35.5.4 emi interface there are 2 emi modes: mode no sdram (register bit emi_configpadlogic[11]=0): the reference is clock cpu_proclk rising edge; mode sdram (register bit emi_configpadlogic[11]=1): outputs (cpu_adr, cpu_data, cpu_rw and commands) are driven by clock cpu_proclk falling edge and inputs (memory read data) are latched with clock cpu_proclk rising edge; symbol parameter min. typ. max. units notes t chav cpu_addr access time -4.0 4.0 ns t clsv strobe output delay time (from cpu_proclk falling) -4.0 4.0 ns t chsv strobe output delay time -4.0 4.0 ns t rdvch read cpu_data setup time 5.0 ns t chrdx read cpu_data hold time 0 ns t chwdv write cpu_data output delay time 0.0 4.0 ns t chrsv "remaining strobes" output delay time -1.0 4.0 ns t wvch cpu_wait setup time 5.0 ns t chwx cpu_wait hold time 0.0 ns table 125 emi interface timing values figure 201 emi interface timing definitions for mode no sdram t chav t clsv t chsv t chrdx t rdvch t chwdv t chrsv t wvch t chwx cpu_adr[20:0] cpu_ras1, cpu_cas[1:0], cpu_be[1:0], cpu_ce[3:0] and cpu_oe cpu_data[15:0] (write) cpu_wait cpu_proclk cpu_data[15:0] (read) cpu_rw
c o n f i d e n t i a l STI5518 35 electrical specifications 7170179 d 287/294 35.5.5 tap interface figure 202 emi interface timing definitions for mode sdram symbol parameter (default reference is tck rising edge) min. typ. max. units notes t tivtch input setup time 4 ns t tchtix input hold time 4 ns t tchtov output delay time (reference tck falling edge) 15 ns table 126 tap timing values figure 203 tap timing definitions t wvch t chwx t chav t chwdv t chrsv cpu_adr[20:0] cpu_ras1, cpu_cas[1:0], cpu_be[1:0], cpu_ce[3:0] and cpu_oe cpu_data[15:0] (write) cpu_wait cpu_proclk cpu_rw t chrdx t rdvch cpu_data[15:0] (read) t chsv t chtix t tivtch t tchtov tck tdi, tms tdo
c o n f i d e n t i a l 35 electrical specifications STI5518 288/294 7170179 d 35.5.6 link interface 35.5.7 i 2 s interface symbol parameter (default reference is b_bclk falling edge) min. typ. max. units notes t ldvlch input setup time 2 ns t lchldx input hold time 2 ns table 127 link interface timing values figure 204 link interface timing definitions symbol parameter min. typ. max. units notes t i2ssetup input setup time 4.5 ns t i2shold input hold time 1 ns table 128 i 2 s interface timing values figure 205 i 2 s interface timing definitions t ldvlch t lchldx b_bclk b_data, b_flag b_bclk b_data, b_flag, b_wclk, b_sync t i2ssetup t i2shold
c o n f i d e n t i a l STI5518 35 electrical specifications 7170179 d 289/294 35.5.8 parallel interface 35.5.9 audio interface symbol parameter min. typ. max. units notes tsetup input data setup time 3 ns thold input data hold time 8 ns treq_to_str request to rising input strobe time 0 ns tstr_to_req rising input strobe to request inactive time 5 35 ns table 129 parallel interface timing values figure 206 parallel interface timing definitions symbol parameter min. typ. max. units notes t sclpd sclk falling edge to data valid 10 ns t scllr sclk falling edge to lrclk hold time 10 ns table 130 audio timing values figure 207 audio timing definitions para_str para_data[7:0] para_req tperiod tstr_to_req treq_to_str thold data 1 data 2 data 3 data 4 data 2048 tsetup (input) (input) (output) t sclpd pcm data (out) sclk t scllr lrclk (input)
c o n f i d e n t i a l 35 electrical specifications STI5518 290/294 7170179 d 35.5.10 atapi interface symbol parameter (default reference is dio rising edge) min. typ. max. units notes t ad_to_diow address setup time (reference is diow falling edge) 30 240 ns t ad_to_dior address setup time (reference is dior falling edge) 30 240 ns t dio_to_ad address hold time 10 220 ns t d_setup data in setup time 15 ns t d_hold data in hold time 5 ns t d_valid data output delay time 15 ns table 131 atapi interface timing values figure 208 atapi interface timing definitions t d_valid data in (read atapi) dior (read) diow (write) address (input) t ad_to_dio data out (write atapi) t d_hold t d_setup t dio_to_ad
c o n f i d e n t i a l STI5518 36 package mechanical data 7170179 d 291/294 36 package mechanical data theSTI5518 is packaged in a 208-pin plastic quad flat pack figure 209 pqfp208 schematic dimensions millimeters inches minimum typical maximum minimum typical maximum a 4.10 0.0161 a1 0.25 0.010 a2 3.20 3.40 3.60 0.126 0.134 0.142 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 d 30.60 1.205 d1 28.00 1.102 d3 25.50 1.004 e 0.50 0.020 e 30.60 1.205 e1 28.00 1.102 e3 25.50 1.004 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.30 0.051 k0 (min.), 7 (max.) table 132 pqfp208 dimensions pin 1 identification e3 e1 e d3 d1 d b e a1 a2 l k c l1 0.004 0.10mm seating plane 208 157 156 104 53 52 1 105
c o n f i d e n t i a l 37 revision history STI5518 292/294 7170179 d 37 revision history 37.1 changes for rev d the corrections made to STI5518 datasheet rev b to create rev d are given in the table below. rev c was an internal revision control, and no changes were made to the document 37.2 changes for rev c internal revision control, no changes to document. 37.3 changes for rev b the corrections made to STI5518 datasheet rev a to create rev b are given in the table below. change description chapter 2: pin data on page 15 pin (118) name cpu_ram_clk is replaced by cpu_proclk (previously, both these names were used for pin 118). section 35.5.4: emi interface on page 286 table 37: list of strobes used for all emi configurations on page 68 clarified peripheral/dram combinations in bank configuration column. chapter 11: test access port on page 88 added register for silicon cut identification. section 13.3: dvb-ci mode (optional) on page 94 new section (optional) for set-top box applications. section 13.5: atapi interface on page 97 clarification of atapi drive speed. chapter 20: digital encoder on page 187 removed references containing "non-interlaced" (no longer required) and deleted register bit name nintrl. chapter 22: double triple video dac on page 216 updated sentence (in para 3): current-sources provide .... chapter 31: synchronous serial controller on page 265 ssc can be master or slave; added section 31.9: i2c hardware configuration on page 271. chapter 35: electrical specifications on page 278 new characterizations. table 133 rev b to rev d changes change description cover page revised text and modified features: cpu frequency 80 mhz, macrovision (optional). section 1.4: audio decoder on page 11 dolby digital, mpeg-1: added layer iii to description. table 1: pins sorted by function on page 16 and table 2: pins sorted by number on page 20 pin numbers 114 and 116 changed to i/o type. added main and alternate functions to pins 1, 2, 3, 187, 188. table 1: pins sorted by function on page 16 and table 2: pins sorted by number on page 20 alternate functions yc[7:0] are outputs. table 1: pins sorted by function on page 16 and table 2: pins sorted by number on page 20 alternate functions for pins 16 - 19 updated. section 3.5: timers on page 30 erroneous name procclockout replaced by cpu_proclk chapter 5: interrupt system on page 45 corrected interrupt numbers in table 34: STI5518 interrupt assignments on page 50 table 35: STI5518 memory map on page 52 removed unused variable mpegdma2baseaddress section 7.1: external memory on page 56 updated shared sdram memory size . table 134 rev a to rev b changes
c o n f i d e n t i a l STI5518 37 revision history 7170179 d 293/294 section 7.3: caching on page 56 updated complete section. sub- section 8.3.2: sdram on page 75 erroneous name procclockout replaced by cpu_proclk table 41: default configuration on page 80 emi default device type changed to ? 000 ? (peripheral). chapter 10: diagnostic controller on page 83 erroneous names triggerin replaced by trigger_in, and triggerout by trigger_out. chapter 11: test access port on page 88 removed text concerning "... for cut a0, the value is 0x20 ...". section 13.2: serial interface on page 93 updated signal names referring to serial bus. section 13.4: parallel interface on page 95 modified text and figure 38 and figure 39 on page 96 . section 13.5: atapi interface on page 97 added 5th. paragraph: ...accessed through bank 1 of cpu .... section 14.4: detailed description on page 109 sub- section 14.4.1: input interface : serial bus names updated. section 14.4: detailed description on page 109 sub- section 14.4.2: nrss interface : serial bus names updated. section 14.4, sub-section not equal filtering on page 119 added first paragraph: ...used only in dvb, not in dss. section 14.6: hard disk drive buffer control on page 132 added this new section. chapter 19: sdram block move on page 186 removed register usd_bsk from table 96: sdram block move registers on page 186 . section 20.4: master mode on page 192 added section. section 20.7: subcarrier generation on page 199 modified section. figure 154: double triple video dac schematic on page 216 updated signal and block names. section 22.5: output-stage adaptation and amplification on page 218 modified section. figure 157: audio decoder block-diagram on page 221 added mp3 block to diagram. section 23.7, sub-section mp3 decoding mode on page 228 removed references to 8 khz and 11.025 khz. figure 165: mp3 decoding flow on page 228 new diagram for mp3 flow. section 23.8: pcm output on page 229 modified text in sub-section output configurations on page 229 concerning configuration 2 & 3 and associated diagram in figure 166 . section 23.9: spdif output on page 233: overview added text regarding register aud_pcmconf . chapter 25: clock generator on page 242 deleted section "audio clock frequency synthesizer". section 25.3: pcm clock on page 244 updated text and table values. section 29.2: smartcard clock generator on page 252 clarified programming of register sci_n_clkval. figure 189: clock and data relationships on page 267 changed value of clkphase to 0 in figure and in text. chapter 35: electrical specifications on page 278 new characterizations. table 118: dc electrical characteristics on page 278 re-formatted (tables 117 & 118)and updated current consump- tion and v ih max. value. table 120: current consumption with st20 running at 81.0 mhz on page 279 added table. figure 200: emi interface timing definitions on page 284 updated signal names. figure 206: parallel interface timing definitions on page 289 corrected definition of t str_req (see also figure 38 ). change description table 134 rev a to rev b changes
c o n f i d e n t i a l STI5518 294/294 7170179 d information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized fo r use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com

▲Up To Search▲

Price & Availability of STI5518

	To Download STI5518 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .